KSZ9031 | Microchip Technology

Overview

  • Automotive:Yes
  • DownstreamPorts:1
  • Energy Efficient Ethernet:No
  • EtherCAT:No
  • Port Speed:10/100/1000Mbps
  • Fiber Support:No
  • HP Auto MDIX:Yes
  • On-Chip Termination:Yes
  • InterfaceUpStream:MII/RGMII/GMII
  • Internal Regulator:Yes
  • LinkMDCableDiag:Yes
  • MACsec:No
  • Supply Voltages:3.3
  • SyncE:No
  • Temperature Range Max:105
  • Temperature Range Min:-40
  • Digital I/O Voltage: 1.8/2.5/3.3
  • WakeonLAN:Yes
  • IEEE 1588 v2:No
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  • Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet transceiver
  • KSZ9031Mxx feature GMII/MII standard interface with 3.3V/2.5V/1.8V tolerant I/Os
  • KSZ9031Rxx feature RGMII timing supports on-chip delay according to RGMII Version 2.0, with programming options for external delay and making adjustments and corrections to TX and RX timing paths
  • GMII/MII/RGMII with 3.3V/2.5V/1.8V tolerant I/Os
  • Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full)
  • On-chip termination resistors for the differential pairs
  • On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core
  • Jumbo frame support up to 16KB
  • 125MHz Reference Clock Output
  • Energy-detect power-down mode for reduced power consumption when the cable is not attached
  • Wake-on-LAN (WOL) support with robust custom-packet detection
  • AEC-Q100 qualified for automotive applications (KSZ9031RNXUB-VAO, KSZ9031RNXVB-VAO)
  • Programmable LED outputs for link, activity, and speed
  • Baseline wander correction
  • LinkMD® TDR-based cable diagnostic to identify faulty copper cabling
  • Parametric NAND tree support to detect faults between chip I/Os and board
  • Loopback modes for diagnostics
  • Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation
  • Automatic detection and correction of pair swaps, pair skew, and pair polarity
  • MDC/MDIO management interface for PHY register configuration
  • Interrupt pin option
  • Power-down and power-saving modes
  • Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator)
  • VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
  • Transceiver (AVDDH): 3.3V or 2.5V (commercial temp)
  • Available in 48-pin QFN (7mm x 7mm) and 64-pin QFN (8mm x 8mm) packages
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    KSZ9031
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