dsPIC33CK256MP710 | Microchip Technology

Overview

  • CPU Type:dsPIC® DSC
  • CPU Speed Max MHz (megahertz):100
  • Program Memory Size (KB):256
  • Multiple Flash Panels:True
  • Direct Memory Access (DMA) Channels:8
  • Temp. Range Min.(C°):-40
  • Temp. Range Max.(C°):150
  • Operation Voltage Min.(V):3
  • Operation Voltage Max.(V):3.6
  • Pin Count:100
  • Low Power:No
  • Number of Comparators:6
  • ADC Modules:5
  • ADC Channels:28
  • ADC Resolution Max:12
  • ADC Sampling Rate (ksps):3500
  • Number of DACs:6
  • DAC outputs:2
  • Max DAC Resolution (bits):12
  • Hardware RTCC:No
  • Motor Control PWM Channels:24
  • SMPS PWM Channels:24
  • Number of PWM Time Bases:21
  • Output Compare Channels:20
  • USB Interface:None
  • Number of CAN Modules:2
  • Type of CAN module Max:CAN-FD
  • Crypto Engine:No
  • Quadrature Encoder Interface (QEI):3
  • Segment LCD:0
  • LCD/Graphics Interface:No
  • Configurable Logic Cell Modules (CLC /CCL):8
  • Peripheral Pin Select (PPS)/Pin Muxing:Yes
  • Supported in MPLAB Code Configurator:Yes
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    Operating Conditions
  • 3.0V to 3.6V, -40ºC to +125ºC, DC to 100 MHz
  • 3.0V to 3.6V, -40ºC to +150ºC, DC to 70 MHz
    dsPIC33CK DSC Core
  • Up to 256 KBytes of Program Flash with ECC
  • Up to 128 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
  • Code efficient (C and Assembly) CPU architecture designed for real-time applications
  • 5 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
  • Single-cycle, mixed-sign 32-bit MUL
  • Fast 6-cycle hardware 32/16 and 16/16 DIV
  • Dual 40-bit fixed point Accumulators (ACC) for DSP operations
  • Single-cycle MAC/MPY with dual data fetch and result write-back
  • Zero overhead looping support
    Core Independent Touch
  • Uses Peripheral Trigger Generator (PTG) and High-speed ADCs
  • Ready-to-use touch library support in MPLAB Code Configurator (MCC)
    Embedded Security
  • CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
  • Flash OTP by ICSP Write Inhibit to configure entire Flash as OTP
  • User OTP
  • Enables implementing robust security use cases together with CryptoAuthentication and CryptoAutomotive devices such as:
  • Secure Boot
  • Secure Firmware Upgrade
  • Secure Communication
  • Node Authentication and more
    High-Speed PWM Module
  • Up to 12 independent PWM pairs (24 total outputs) with up to 250ps resolution
  • Dead-time insertion for rising and falling edges and dead-time compensation support
  • Clock chopping for high-frequency operation
  • Fault and current limit inputs
  • Flexible trigger configuration for ADC triggering
    Advanced Analog Features
  • 5x 12-bit 3.5 MSPS ADC Modules each with 4 dedicated SARs and 1 shared SAR cores (5 S&Hs)
  • Up to 28 ADC input channels
  • 5 digital comparators for reducing CPU overhead
  • 5 oversampling filters for increased resolution
  • Up to 6 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
  • Up to 3 op amps with internal connection to ADC Module
    Timer/Counters/Output Compare/Input Capture
  • 24x 16-bit timer/counters (up to 12x 32-bit)
  • 14 PWM or Output Compare (OC) outputs
  • 9 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules
  • 3 Quadrature Encoder Interface (QEI) modules for optical encoder support
  • Peripheral Trigger Generator (PTG) for scheduling complex sequences
    Communication Interfaces
  • 3 UARTs (15 Mbps) with automated protocol handling for LIN2.2, DMX and IrDA®
  • 3x 4-wire SPI/I2S, up to 40 MHz operation on SPI with dedicated pins
  • 3 I2C Modules (up to 1 Mbps) with SMBus support
  • 2 CAN Flexible Data Rate (CAN-FD) Module ("7xx devices only)
  • 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
  • 8 DMA channels supporting UART, SPI, ADC, CAN-FD, IC, OC and Timer data transfers
    Clock and Power Management
  • On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators
  • Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
  • Fail-Safe Clock Monitor (FSCM) with 8 MHz Back-up Fast RC (BFRC) oscillator
  • Low-Power management modes - Sleep, Idle and Doze
  • Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)
    Debugger Development Support
  • In-Circuit and in application programming and debug support (ICSP)
  • On-chip debug trace buffer and run-time watch with 3 complex and 5 simple breakpoints
  • IEEE 1149.2 (JTAG) boundary scan support
    Safety Features
  • Dead-Man Timer (DMT) safety feature clocked by instruction fetches
  • Watch Dog Timer (WDT)
  • CodeGuard™ security for program Flash
  • Programmable Cyclic Redundancy Check (CRC)
  • Flash ECC Fault Injection testing feature
  • Flash OTP by ICSP™ write inhibit
  • RAM Memory Built-In Self Test (MBIST)
  • Two-Speed Start-up
  • Fail-Safe Clock Monitoring (FSCM)
  • Backup FRC (BFRC)
  • Virtual Pins for Redundancy and Monitoring
  • Multiple redundant clock sources
  • I/O Port read-back
  • Analog peripherals redundancies
  • Hardware traps
  • SFR locks
  • Write protection
  • Shadow working registers
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dsPIC33CK256MP710
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