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XIP1213B


XIP1213B from Xiphera is a balanced Intellectual Property (IP) core implementing the MACsec protocol as standardized in IEEE Std 802.1AE-2018. XIP1213B uses Advanced Encryption Standard with 256 bits long key in Galois Counter Mode (AES-GCM) to protect data confidentiality, data integrity and data origin authentication. The cipher suite is denoted either as GCM-AES-XPN-256 if the eXtended Packet Numbering (XPN) is in use, or as GCM-AES-XPN-256 if XPN is not in use. Both GCM-AES-256 and GCM-AES-XPN-256 use Xiphera’s IP core XIP1113B as the underlying building block for AES-GCM. XIP1213B is best suited for traffic on 1 Gbps links, and can be deployed using low-cost FPGA families. XIP1213B can also in selected cases be retrofitted to existing FPGA designs without requiring a board re-spin, either if there are enough FPGA resources available or if a pin-compatible FPGA with additional resources can be used.


Features and Benefits


  • Moderate resource requirements: The entire XIP1213B requires 24402 4-input Lookup Tables (4LUTs) (Microchip® PolarFire® ), and does not require any multipliers or DSPBlocks in a typical Microchip® FPGA implementation
  • Performance: XIP1213B achieves a high throughput3 , for example 686.24+ Gbps in Microchip® PolarFire®
  • Standard Compliance: XIP1213B is fully compliant with the MACsec protocol as standardized in IEEE Std 802.1AE-2018. The cipher suite (GCM-AES-256 or GCM-AES-XPN-256) is fully compliant with the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard
  • Test Vector Compliance: XIP1213B passes the relevant test vectors specified in Annex C of IEEE Std 802.1AE-2018
  • 32-bit FIFO Interfaces ease the integration of XIP1213B with other Microchip® FPGA logic and/or control software

Licensing Options


For additional information contact: sales@xiphera.com or visit XIPHERA

Documentation


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