IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as Microchip® LibreSoC SmartDesign Ready component and hence can be easily integrated in SmartDesign system.
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Features and Benefits
- Supports LS (1.5 Mbps), FS (12 Mbps) and HS (480 Mbps) modes.
- Supports Control, Bulk and Interrupt transfers.
- Contains two different interface for Control Port and Data Port to improve Clock Domain Crossing (CDC) performance.
- Supports Asynchronous AXI clock interface.
- Configurable memory depth.
Licensing Options
For additional information, visit SLS webpage or contact SLS through info@slscorp.com email.
Documentation
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