In this IP core, processor is responsible to manage transfer for endpoint 0 (default control endpoint). IP core has AXI4 interface by which processor can communicate with IP core. This provides flexibility to the user to manage enumeration data. To transfer data over non-zero endpoint, user just needs to manage this FIFO interface. User can write down VHDL, Verilog or System Verilog code to manage this FIFO interface
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Features and Benefits
- It supports SuperSpeed Plus (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
- Uses Microchip PolarFire Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.1.
- Provides ULPI interface to interact with external USB 2.0 PHY.
- Capable to support up to 31 endpoints (1 default control endpoint, 15 IN endpoints and 15 OUT endpoints).
- Allows to select number of buffers per endpoint based on the requirement.
Licensing Options
For additional information, visit SLS webpage or contact SLS through info@slscorp.com email.
Documentation
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| eusb_3-1-_gen2_device_controller | Link |