The SpaceWire Interface IP Core provides a SpaceWire interface which is fully compliant to the ECSS-E-ST-50-12C Rev.1 SpaceWire standard. It includes generics to enable it to be targeted at both ASIC and FPGA implementations. The IP is comprised of a serial encoder and decoder, initialisation controller state machine, data FIFOs with receive flow control counters, and a broadcast interface for Time-code and distributed interrupt code distribution. The packet and broadcast interfaces are AXI4‑Stream encoded. A DMA Controller IP Core with AMBA bus interface is provided with the core supporting integration with embedded processor or system on chip designs.
Log in to myMicrochip to access tools and benefits. Sign up in just one minute.
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest! Update Here
Stay in the loop with the latest from Microchip! Update your profile while you are at it. Update Here
Complete your profile to access more resources.Update Here!
true
Features and Benefits
- Fully compliant with the SpaceWire standard, ECSS-E-ST-50-12C Rev.1
- Delivered as synthesisable VHDL source code in obfuscated or clear code format
- AXI4-Stream packet data interfaces with optional programmable DMA controller
- Reference designs provided for all Microchip families including RTG4 and PolarFire
Licensing Options
For additional information, contact enquiries@star-dundee.com or visit STAR-Dundee
Documentation
|
Title
|
||
|---|---|---|
| spacewire-interface | Link |