The MIV_RV32 is a processor core designed to implement the RISC-V instruction set for use in Microchip FPGAs.The core includes the industry standard JTAG interface to facilitate debug access. Three optional bus interfaces areavailable for peripheral and memory accesses: AHB, APB3, and AXI, which can be configured as AXI3 or AXI4.
Log in to myMicrochip to access tools and benefits. Sign up in just one minute.
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest! Update Here
Stay in the loop with the latest from Microchip! Update your profile while you are at it. Update Here
Complete your profile to access more resources.Update Here!
true
Features and Benefits
Designed for low power FPGA soft-core implementations
Licensing Options
Free with any Libero License
Documentation
|
Title
|
||
|---|---|---|
| MIV_RV32 v3.1 User Guide | Download | |
| MIV_RV32 v3.1 Migration Guide | Download | |
| MIV_RV32 v3.1.2 Release Notes | Download | |
| PolarFire_MIV_RV32IMC_v21 | Download | |
| RISC-V External Debug Support | Download | |
| Supplementary RUP Information for MIV_RV32 v3.0 | Download | |
| The RISC-V Instruction Set Manual | Download | |
| The RISC-V Instruction Set Manual | Download | |
| MIV_RV32 v3.0 Handbook | Download | |
| MI-V RV32 Migration Guide | Download | |
| RN0236 Release Notes MIV_RV32 v3.0 | Download |