The MIV_ESS v2.0 is a Mi-V ecosystem IP core available for the Microchip FPGA and System-on-Chip (SoC) FPGAdevice families. The core is a multi-featured, highly-configurable, Extended Subsystem (ESS), which supports bothbootstrap and base peripherals. It is specifically designed to use with the MIV_RV32 soft processor.
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Features and Benefits
- Designed for low-power FPGA implementations.
- Highly configurable, compact, and extended subsystem solution for the MIV_RV32 soft proce
- APB interface to access subsystem memory-mapped peripherals.
- Seven optional external APB interfaces to connect additional peripheral
Licensing Options
Free with any Libero License