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CoreSPI

CoreSPI is a controller core designed for synchronous serial communication using a Motorola, TI, orNSC serial peripheral interface (SPI). The core is parameterized to allow user specification of theoperating mode, FIFO depth, and frame width


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Features and Benefits

  • SPI clock rate configurable
  • From PCLK/512 to PCLK/2 in steps of 2
  • Maximum data rate of PCLK/2 in Master mode and PCLK/8 in Slave mode.
  • SPI protocol configurable
  • Master and slave operation
  • Slave select behavior configurable during Idle cycles

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    CoreSPI_HB.pdf Download