We detect you are using an unsupported browser. For the best experience, please visit the site using Chrome, Firefox, Safari, or Edge. X
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest! Update Here
Stay in the loop with the latest from Microchip! Update your profile while you are at it. Update Here
Complete your profile to access more resources.Update Here!
Item Qty
Your cart is empty.
❮ ❯

CORERISCV_AXI4

CoreRISCV_AXI4 is a softcore processor designed to implement the RISC-V instruction set for use in Microchip FPGAs. The processor is based on the Coreplex E31 designed by SiFive, containing a high-performance single-issue, in-order execution pipeline E31 32-bit RISC-V core


Buy Now

Features and Benefits

  • Designed for low power ASIC microcontroller and FPGA soft-core implementations.
  • Integrated 8Kbytes instructions cache and 8 Kbytes data cache.
  • A Platform-Level Interrupt Controller (PLIC) can support up to 31 programmable interrupt with a single priority level.
  • Supports the RISCV standard RV32IM ISA.
  • On-Chip debug unit with a JTAG interface.
  • Two external AXI interfaces for IO and memory

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    HB0761: CoreRISCV_AXI4 v2.0 Handbook Download