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COREEDAC

CoreEDAC produces Microchip field programmable gate array (FPGA)-optimized error detection andcorrection (EDAC) logic based on user-defined parameters. For ease of use, the core enablesgeneration of logic integrated with on-chip RAM.


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Features and Benefits

  • Parameterizable RTL generator
  • Modes of operation:
  • EDAC with internal RAM. EDAC RAM generation with optional background scrubbing circuitry
  • EDAC encoder and decoder generation. The mode can be used to apply EDAC encoder anddecoder to external memories.
  • Flexible user data size from 4 to 64 bits. This corresponds to a codeword size from 8 to 72 bits
  • Option to suppress write-back during the scrubbing session
  • Optional triple EDAC redundancy

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    CoreEDAC_HB.pdf Download