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COREAXI4INTERCONNECT

The AMBA AXI4 Interconnect core connects one or more AXI memory-mapped master devices to one ormore memory-mapped slave devices. The AMBA AXI protocol supports high-performance, highfrequency system designs. Inside the AXI Interconnect core, theAXI4 Crossbar core routes the traffic between the Slave Ports (SP) and Master Ports (MP). The convention followed here is that the master-side ports connect to external upstream masters, while the slave-side ports connect to external downstream slaves. 


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Features and Benefits

 

  • Supports high-Bandwidth and low-latency designs. 
  • Separate address/control and data phases.
  • Supports unaligned data transfers, using byte strobes.
  • Uses burst-based transactions with only the start address issued.
  • Separate read and write data channels, which provides low-cost Direct Memory Access (DMA).
  • Supports multiple outstanding read/write transactions.
  • Supports out-of-order read transaction completion.
  • Permits easy addition of register stages to provide timing closure.

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    Licensing Options

    Free with any Libero License

    Documentation

    Title
    CoreAXI4Interconnect User Guide Download