The ALSE Aurora 8B/10B IP Core is a lightweight, high-speed, and low latency serial protocol suitable for chip-to-chip, board-to-board and backplane applications using Transceivers. IP provides an efficient way to interconnect a Microchip FPGA with other vendors FPGA.
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Features and Benefits
- Full Duplex and Simplex.
- Up to 16 Transceivers physical lanes.
- Link Rate up to Device maximum transceiver rate.
- 8B/10B encoding.
- Framing and Streaming interfaces.
- User Flow Control (UFC).
- Native Flow Control (NFC, immediate/completion modes).
- Additional CRC for PDU Frames.
- Clock compensation Sequence Generation.
- Per lane polarity inversion, skew compensation.
- Avalon-ST / AXI-like Streaming user interfaces.
- Provided with Hardware Reference designs, QIP files, SDC constraints, Simulation environment.
Licensing Options
For additional information, info@alse-fr.com or visit ALSE
Documentation
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