ModelSim ME and ModelSim Pro ME

Version 11.8 of Libero^® SoC Design Suite comes with a new simulator: ModelSim Pro ME, which provides enhanced simulation capabilities. With this new edition of the simulator, we introduce mixed-language simulation for Verilog, SystemVerilog and VHDL.

Versions 11.8 or later of Libero SoC Design Suite include ModelSim Pro ME. Siemen’s (formerly Mentor) ModelSim simulator is a source-level verification tool, allowing you to verify HDL code line by line. You can perform simulation at all stages in the Libero software design flow: behavioral (pre-synthesis), structural (post-synthesis) and back annotated/dynamic. Coupled with the most popular HDL debugging capabilities in the industry, ModelSim is known for delivering high performance, ease of use and outstanding product support.

An easy-to-use graphical user interface allows you to quickly identify and debug problems, aided by dynamically updated windows. For example, selecting a design region in the structure window automatically updates the source, signals, process and variables windows. These cross-linked ModelSim windows create an easy-to-use debug environment. Once a problem is found, you can edit, recompile and re-simulate without leaving the simulator. ModelSim fully supports current VHDL and Verilog language standards and you can simulate behavioral, RTL and gate-level code separately or simultaneously. ModelSim supports all of our FPGA libraries, ensuring accurate timing simulations.

The comprehensive user interface makes efficient use of desktop real estate. The intuitive arrangement of interactive graphical elements (windows, toolbars, menus and more) makes it easy to view and access the many powerful capabilities of ModelSim. The result is a feature-rich user interface that is easy to use and quickly mastered.