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Key Benefits Product Table Documentation

Axcelerator FPGAs

The Axcelerator Family of Antifuse FPGAs

Axcelerator, our antifuse family of FPGAs, offers high performance and unprecedented design security at densities of up to 2 million equivalent system gates.

Utilizing our AX architecture, Axcelerator devices have several system-level features, such as embedded SRAM (with embedded FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing and the ability to carry logic.

Developed with a CMOS antifuse process technology based on 0.15 µm and seven layers of metal, Axcelerator devices offer a level of performance previously only available in ASIC technology.

Key Benefits of Axcelerator FPGAs

350 MHz system performance
500+ MHz internal performance
500+ MHz embedded FIFOs
PLL output up to 1 GHz and eight PLLs per device
Six levels of logic at 156+ MHz
1.5V, 1.8V, 2.5V and 3.3V mixed-voltage operation
Eight Input/Output (I/O) banks per device
Eight global clocks per device
4.5 kbits variable-aspect RAM blocks with built-in FIFO control
Intelligent low-power operation
Secure programming technology that prevents reverse engineering and design theft
Available in military temperature grades

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Products

Device	AX125	AX250	AX500	AX1000	AX2000
Capacity (in Equivalent System Gates)	125,000	250,000	500,000	1,000,000	2,000,000
Typical Gates	82,000	154,000	286,000	612,000	1,060,000
Equivalent Logic Elements	672	1,408	2,688	6,048	10,752
Modules
Register (R-cells)	672	1,408	2,688	6,048	10,752
Combinatorial (C-cells)	1,344	2,816	5,376	12,096	21,504
Maximum Flip-Flops	1,344	2,816	5,376	12,096	21,504
Embedded RAM/FIFO
Number of Core RAM Blocks	4	12	16	36	64
Total Bits of Core RAM	18,432	55,296	73,728	165,888	294,912
Clocks (Segmentable)
Hardwired	4	4	4	4	4
Routed	4	4	4	4	4
PLLs	8	8	8	8	8
I/Os
I/O Banks	8	8	8	8	8
Maximum User I/Os	168	248	336	516	684
Maximum LVDS Channels	84	124	168	258	342
Total I/O Registers	504	744	1,008	1,548	2,052
Speed Grades	Std., -1, -2	Std., -1, -2	Std., -1, -2	Std., -1, -2	Std., -1, -2
Temperature Grades	C, I	C, I, M	C, I, M	C, I, M	C, I, M
Package
PQFP		208	208
BGA				729
FBGA	256, 324	256, 484	484, 676	484, 676, 896	896, 1152
CQFP		208, 352	208, 352	352	256, 352
CCGA/LGA				624	624

C = Commercial, I = Industrial, A = Automotive

Documentation

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Document Category	Title	Date
Data Sheets	Axcelerator Family FPGAs Product Brief	16 Jan 2003
Product Selector Tools	Antifuse Product Catalog	29 Aug 2013
Data Sheets	Axcelerator Family FPGAs Datasheet	30 Sep 2024
Data Sheets	PD3068: Package Mechanical Drawings Datasheet	30 Jan 2025
Packaging Specifications	Package Thermal Characteristics and Weights	05 Jun 2003
Packaging Specifications	Hermetic Package MechanicalConfiguration	15 Jan 2003
Product Brief	Power Estimator	14 Oct 2022
	Overview of Antifuse Device Security- White Paper	07 Oct 2022
Data Sheets	DC-DC Regulator Guide for Microsemi FPGAs and SOC FPGAs	23 Sep 2022
Application Notes	AC163: Axcelerator Carry-Connect Macros App Note	12 Jan 2003
Application Notes	AC164: Axcelerator Family Memory Blocks App Note	12 Jan 2003
Application Notes	AC175: Axcelerator Family PLL and Clock Management App Note	13 Jan 2003
Application Notes	AC209: Axcelerator Family Footprint Compatibility App Note	15 Jul 2004
Application Notes	AC182: Axcelerator I/O Selection Guide App Note	07 Aug 2003
Application Notes	AC184: Migrating from Engineering Silicon to Production Devices for the Axcelerator Family App Note	18 Aug 2003
Application Notes	AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note	16 Jul 2003	Design Files
Application Notes	AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note	22 Jul 2004	Design Files
Application Notes	AC228: EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller App Note	28 Mar 2005
Application Notes	AC218: Using Axcelerator RAM as Multipliers App Note	23 Feb 2005
Application Notes	AC249: I/O Features in Axcelerator Family Devices App Note	07 Aug 2003	Design Files
Application Notes	AC212: Designing a SuperClock with an Axcelerator Device App Note	21 Sep 2004	Design Files
Application Notes	AC210: Laser Range Finder Using Actel	21 Jul 2004	Design Files
Application Notes	AC217: IEEE Standard 1149.1 (JTAG) in the Axcelerator Family App Note	08 Feb 2005
Application Notes	AN 4535 : Programming Antifuse Devices	23 Jun 2005
Application Notes	AC308: Antifuse MetaReport AN	06 May 2013
Application Notes	AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note	20 Jul 2003	Design Files
Application Notes	AC173: Differences Between RTAX-S/SL and Axcelerator App Note	25 May 2003
Application Notes	AC288: Using LVDS for Microsemi Axcelerator and RTAX-S/SL Devices App Note	13 Oct 2004
Application Notes	AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note	22 Jun 2006	Design Files
Application Notes	AC354: Core8051s Debugging in Axcelerator and RTAX-S Device	22 Sep 2010	Design Files
Application Notes	AC183: Using Global Resources in Actel's Axcelerator Family App Note	07 Aug 2003
Application Notes	AC379: Advanced Static Timing Analysis Using SmartTime App Note	30 Oct 2011
	AC168 : Implementation of Security in Antifuse FPGAs	07 Oct 2022
Application Notes	AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment Application Note	18 May 2004
Application Notes	AC276: Board Level Considerations for Microsemi FPGAs App Note	15 Jan 2003
Application Notes	AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note	13 Feb 2003	Design Files
Application Notes	AC170: Prototyping RTAX-S Using Axcelerator Devices App Note	25 May 2003
Application Notes	Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note	02 Aug 2011	Design Files
Board Design Files	Axcelerator Commercial IBIS Model (UNIX gzip)	06 Mar 2005
Board Design Files	Axcelerator Industrial IBIS Model (UNIX gzip)	06 Mar 2005
Board Design Files	Axcelerator Military IBIS Model (UNIX gzip)	06 Mar 2005
Board Design Files	AX125-CS180 BSDL	28 Mar 2005
Board Design Files	AX125-FG324 BSDL	28 Mar 2005
Board Design Files	AX250-CQ208 BSDL	28 Mar 2005
Board Design Files	AX250-FG256 BSDL	28 Mar 2005
Board Design Files	AX250-FG484 BSDL	28 Mar 2005
BSDL Files	AX250_CQ352.BSDL	10 Oct 2019
Board Design Files	AX1000-BG729 BSDL	28 Mar 2005
Board Design Files	AX1000-CG624 BSDL	28 Mar 2005
Board Design Files	AX1000-CQ352 BSDL	28 Mar 2005
Board Design Files	AX250-PQ208 BSDL	28 Mar 2005
Board Design Files	AX500-CQ352 BSDL	28 Mar 2005
Board Design Files	AX500-FG484 BSDL	28 Mar 2005
BSDL Files	AX500_CQ208 BSDL	10 Oct 2019
BSDL Files	AX500_FG676 BSDL	10 Oct 2019
BSDL Files	AX500_PQ208 BSDL	10 Oct 2019
Board Design Files	AX1000-FG484 BSDL	28 Mar 2005
Board Design Files	AX1000-FG896 BSDL	28 Mar 2005
Board Design Files	AX2000-CG624 BSDL	28 Mar 2005
Board Design Files	AX2000-CQ256 BSDL	26 Jul 2006
Board Design Files	AX2000-CQ352 BSDL	28 Mar 2005
BSDL Files	AX1000_FG676 BSDL	10 Oct 2019
BSDL Files	AX2000_FG896 BSDL	10 Oct 2019


Document Category Title Date	Data Sheets Axcelerator Family FPGAs Product Brief 16 Jan 2003
Document Category Title Date	Product Selector Tools Antifuse Product Catalog 29 Aug 2013
Document Category Title Date	Data Sheets Axcelerator Family FPGAs Datasheet 30 Sep 2024
Document Category Title Date	Data Sheets PD3068: Package Mechanical Drawings Datasheet 30 Jan 2025
Document Category Title Date	Packaging Specifications Package Thermal Characteristics and Weights 05 Jun 2003
Document Category Title Date	Packaging Specifications Hermetic Package MechanicalConfiguration 15 Jan 2003
Document Category Title Date	Product Brief Power Estimator 14 Oct 2022
Document Category Title Date	Overview of Antifuse Device Security- White Paper 07 Oct 2022
Document Category Title Date	Data Sheets DC-DC Regulator Guide for Microsemi FPGAs and SOC FPGAs 23 Sep 2022
Document Category Title Date	Application Notes AC163: Axcelerator Carry-Connect Macros App Note 12 Jan 2003
Document Category Title Date	Application Notes AC164: Axcelerator Family Memory Blocks App Note 12 Jan 2003
Document Category Title Date	Application Notes AC175: Axcelerator Family PLL and Clock Management App Note 13 Jan 2003
Document Category Title Date	Application Notes AC209: Axcelerator Family Footprint Compatibility App Note 15 Jul 2004
Document Category Title Date	Application Notes AC182: Axcelerator I/O Selection Guide App Note 07 Aug 2003
Document Category Title Date	Application Notes AC184: Migrating from Engineering Silicon to Production Devices for the Axcelerator Family App Note 18 Aug 2003
Document Category Title Date	Application Notes AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note 16 Jul 2003 Design Files
Document Category Title Date	Application Notes AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note 22 Jul 2004 Design Files
Document Category Title Date	Application Notes AC228: EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller App Note 28 Mar 2005
Document Category Title Date	Application Notes AC218: Using Axcelerator RAM as Multipliers App Note 23 Feb 2005
Document Category Title Date	Application Notes AC249: I/O Features in Axcelerator Family Devices App Note 07 Aug 2003 Design Files
Document Category Title Date	Application Notes AC212: Designing a SuperClock with an Axcelerator Device App Note 21 Sep 2004 Design Files
Document Category Title Date	Application Notes AC210: Laser Range Finder Using Actel 21 Jul 2004 Design Files
Document Category Title Date	Application Notes AC217: IEEE Standard 1149.1 (JTAG) in the Axcelerator Family App Note 08 Feb 2005
Document Category Title Date	Application Notes AN 4535 : Programming Antifuse Devices 23 Jun 2005
Document Category Title Date	Application Notes AC308: Antifuse MetaReport AN 06 May 2013
Document Category Title Date	Application Notes AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note 20 Jul 2003 Design Files
Document Category Title Date	Application Notes AC173: Differences Between RTAX-S/SL and Axcelerator App Note 25 May 2003
Document Category Title Date	Application Notes AC288: Using LVDS for Microsemi Axcelerator and RTAX-S/SL Devices App Note 13 Oct 2004
Document Category Title Date	Application Notes AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note 22 Jun 2006 Design Files
Document Category Title Date	Application Notes AC354: Core8051s Debugging in Axcelerator and RTAX-S Device 22 Sep 2010 Design Files
Document Category Title Date	Application Notes AC183: Using Global Resources in Actel's Axcelerator Family App Note 07 Aug 2003
Document Category Title Date	Application Notes AC379: Advanced Static Timing Analysis Using SmartTime App Note 30 Oct 2011
Document Category Title Date	AC168 : Implementation of Security in Antifuse FPGAs 07 Oct 2022
Document Category Title Date	Application Notes AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment Application Note 18 May 2004
Document Category Title Date	Application Notes AC276: Board Level Considerations for Microsemi FPGAs App Note 15 Jan 2003
Document Category Title Date	Application Notes AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note 13 Feb 2003 Design Files
Document Category Title Date	Application Notes AC170: Prototyping RTAX-S Using Axcelerator Devices App Note 25 May 2003
Document Category Title Date	Application Notes Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note 02 Aug 2011 Design Files
Document Category Title Date	Board Design Files Axcelerator Commercial IBIS Model (UNIX gzip) 06 Mar 2005
Document Category Title Date	Board Design Files Axcelerator Industrial IBIS Model (UNIX gzip) 06 Mar 2005
Document Category Title Date	Board Design Files Axcelerator Military IBIS Model (UNIX gzip) 06 Mar 2005
Document Category Title Date	Board Design Files AX125-CS180 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX125-FG324 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX250-CQ208 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX250-FG256 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX250-FG484 BSDL 28 Mar 2005
Document Category Title Date	BSDL Files AX250_CQ352.BSDL 10 Oct 2019
Document Category Title Date	Board Design Files AX1000-BG729 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX1000-CG624 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX1000-CQ352 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX250-PQ208 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX500-CQ352 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX500-FG484 BSDL 28 Mar 2005
Document Category Title Date	BSDL Files AX500_CQ208 BSDL 10 Oct 2019
Document Category Title Date	BSDL Files AX500_FG676 BSDL 10 Oct 2019
Document Category Title Date	BSDL Files AX500_PQ208 BSDL 10 Oct 2019
Document Category Title Date	Board Design Files AX1000-FG484 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX1000-FG896 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX2000-CG624 BSDL 28 Mar 2005
Document Category Title Date	Board Design Files AX2000-CQ256 BSDL 26 Jul 2006
Document Category Title Date	Board Design Files AX2000-CQ352 BSDL 28 Mar 2005
Document Category Title Date	BSDL Files AX1000_FG676 BSDL 10 Oct 2019
Document Category Title Date	BSDL Files AX2000_FG896 BSDL 10 Oct 2019

Application Notes
Data Sheets
Power Estimator
User Guides
Product Selector Guide

Title	Date
AC163: Axcelerator Carry-Connect Macros App Note	12 Jan 2003
AC164: Axcelerator Family Memory Blocks App Note	12 Jan 2003
AC175: Axcelerator Family PLL and Clock Management App Note	13 Jan 2003
AC209: Axcelerator Family Footprint Compatibility App Note	15 Jul 2004
AC182: Axcelerator I/O Selection Guide App Note	07 Aug 2003
AC184: Migrating from Engineering Silicon to Production Devices for the Axcelerator Family App Note	18 Aug 2003
AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note	16 Jul 2003	Link
AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note	22 Jul 2004	Link
AC228: EMPTY and FULL Flag Behaviors of the Axcelerator FIFO Controller App Note	28 Mar 2005
AC218: Using Axcelerator RAM as Multipliers App Note	23 Feb 2005
AC249: I/O Features in Axcelerator Family Devices App Note	07 Aug 2003	Link
AC212: Designing a SuperClock with an Axcelerator Device App Note	21 Sep 2004	Link
AC210: Laser Range Finder Using Actel	21 Jul 2004	Link
AC217: IEEE Standard 1149.1 (JTAG) in the Axcelerator Family App Note	08 Feb 2005
AN 4535 : Programming Antifuse Devices	23 Jun 2005
AC308: Antifuse MetaReport AN	06 May 2013
AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note	20 Jul 2003	Link
AC173: Differences Between RTAX-S/SL and Axcelerator App Note	25 May 2003
AC288: Using LVDS for Microsemi Axcelerator and RTAX-S/SL Devices App Note	13 Oct 2004
AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note	22 Jun 2006	Link
AC354: Core8051s Debugging in Axcelerator and RTAX-S Device	22 Sep 2010	Link
AC183: Using Global Resources in Actel's Axcelerator Family App Note	07 Aug 2003
AC379: Advanced Static Timing Analysis Using SmartTime App Note	30 Oct 2011
AC168 : Implementation of Security in Antifuse FPGAs	07 Oct 2022
AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment Application Note	18 May 2004
AC276: Board Level Considerations for Microsemi FPGAs App Note	15 Jan 2003
AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note	13 Feb 2003	Link
AC170: Prototyping RTAX-S Using Axcelerator Devices App Note	25 May 2003
Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note	02 Aug 2011	Link

Data Sheets

IBIS Models

BSDL Models

Data Sheets

Title	Date
Axcelerator Family FPGAs Product Brief	16 Jan 2003
Antifuse Product Catalog	29 Aug 2013
Axcelerator Family FPGAs Datasheet	30 Sep 2024
PD3068: Package Mechanical Drawings Datasheet	30 Jan 2025

IBIS Models

Title	Date
Axcelerator Commercial IBIS Model (UNIX gzip)	06 Mar 2005
Axcelerator Industrial IBIS Model (UNIX gzip)	06 Mar 2005
Axcelerator Military IBIS Model (UNIX gzip)	06 Mar 2005

Note:

IBIS Model Usage provides instructions on obtaining max/min source/sink current.
IBIS Background and Usage Application Notes provides signal integrity on PCBs.

BSDL Models

Title	Date
AX125-CS180 BSDL	28 Mar 2005
AX125-FG324 BSDL	28 Mar 2005
AX250-CQ208 BSDL	28 Mar 2005
AX250-FG256 BSDL	28 Mar 2005
AX250-FG484 BSDL	28 Mar 2005
AX250_CQ352.BSDL	10 Oct 2019
AX1000-BG729 BSDL	28 Mar 2005
AX1000-CG624 BSDL	28 Mar 2005
AX1000-CQ352 BSDL	28 Mar 2005
AX250-PQ208 BSDL	28 Mar 2005
AX500-CQ352 BSDL	28 Mar 2005
AX500-FG484 BSDL	28 Mar 2005
AX500_CQ208 BSDL	10 Oct 2019
AX500_FG676 BSDL	10 Oct 2019
AX500_PQ208 BSDL	10 Oct 2019
AX1000-FG484 BSDL	28 Mar 2005
AX1000-FG896 BSDL	28 Mar 2005
AX2000-CG624 BSDL	28 Mar 2005
AX2000-CQ256 BSDL	26 Jul 2006
AX2000-CQ352 BSDL	28 Mar 2005
AX1000_FG676 BSDL	10 Oct 2019
AX2000_FG896 BSDL	10 Oct 2019

Title	Date
Package Thermal Characteristics and Weights	05 Jun 2003
Hermetic Package MechanicalConfiguration	15 Jan 2003
Power Estimator	14 Oct 2022

Title	Date
Overview of Antifuse Device Security- White Paper	07 Oct 2022
DC-DC Regulator Guide for Microsemi FPGAs and SOC FPGAs	23 Sep 2022

The Axcelerator FPGA family is a single-chip, nonvolatile solution offering high performance and unprecedented design security at densities of up to 2 million equivalent system gates. Utilizing the AX architecture, Axcelerator devices have several system-level features, such as embedded SRAM (with embedded FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing and carry logic. The solution is based on a 0.15-μm, seven-layers-of-metal CMOS antifuse process technology and 350-MHz system performance.

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