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Embedded Pulse Per Second (ePPS) Solutions

As 5G wireless networks drive the need for time alignment across today's wired networks, traditional systems are now facing the challenge of accommodating 1 Pulse Per Second (PPS) signals on already crowded backplanes. Our embedded PPS (ePPS) solutions address this issue by overlaying the 1 PPS signal without requiring additional clocks and backplane connections. This cost-effective and reliable technology is now widely adopted by our customers, ensuring optimal performance and synchronization in modern network environments.

Benefits of ePPS Solutions

  • No extra traces are required on the backplane; no upgrade is necessary
  • 1 PPS and clock signals are always aligned automatically
  • Non-ePPS PLLs only see clock rising edges; manipulation of falling edge has no effect
  • Microchip ePPS line card PLLs lock to clock rising edges and decode 1 PPS position

Applications

  • Data center servers (rack and blade)
  • Telecom: 5G, mobile, fronthaul, backhaul
  • Edge computing
  • QSFP optical modules

Standards

  • QSFP-DD MSA
    • Revision 7.1, June 25, 2024
  • OCP NIC 3.0 Design Specification 3
    • Version 1.5.0, September 20, 2024

Featured Products

ZL40268

Low-Skew, Low-Jitter Differential ePPS Fanout Buffer

This clock fanout buffer offers ultra-low additive jitter of just 24 fs and supports frequencies up to 1.5 GHz. Well suited for PCIe® clock trees Gen 1–5, it features eight outputs, hot-swappable capabilities and control via individual output pins or I2C interface.

ZL40241

Low-Skew, Low-Jitter LVCMOS ePPS Fanout Buffer

This LVCMOS clock fanout buffer offers ultra-low additive jitter of 17 fs and supports frequencies up to 200 MHz. It has ten LVCMOS outputs, which can be powered from a 3.3V, 2.5V, 1.8V or 1.5V supply. Output can be synchronously enabled/disabled via an OE pin.

ZL80132B

NetSync ePPS TimeBuffer

Containing dual DPLL clock channels, three DPLLs for advanced modes and five low-jitter synthesizers, its features also include ePPS, fast boot, partial reset and cascading DPLL. This product is well suited for 5G DU/CU server applications with GPS/GNSS synchronization.

ZL80640B

ePPS TimeBuffer

This ePPS TimeBuffer features four inputs and 12 outputs, providing reliable time signal fanout with ePPS and smooth ref-sync locking. Intended for server-based 5G DU/CU applications, it can be integrated into OCP NIC or PCIe daughter cards or deployed in large telecom chassis systems.

OX-221

High-Stability Crystal Oscillator

A high-performance Oven Controlled Crystal Oscillator (OCXO) in a 22 × 25 SMD hermetically sealed package, this device delivers excellent frequency stability, slope and holdover performance for 5G base stations and 1588 applications.

Note: We have three generations of Network Synchronization (NetSync) devices that support ePPS and customer implementations that span multiple platforms.

System Block Diagram

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