PIC24FJ32GP205 | Microchip Technology
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PIC24FJ32GP205

Status: In Production
eXtreme Low Power MCU
Data Sheet:
PDF
PIC24FJ64GP205/GU205 Family
Recommended for Automotive Design
This product is recommended for design into automotive applications. Special ordering codes for automotive grade versions apply. Click on icon for more details.
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Overview

  • CPU Type:16-bit PIC MCU
  • CPU Speed Max MHz (megahertz):16
  • Program Memory Size (KB):32
  • Multiple Flash Panels:False
  • Direct Memory Access (DMA) Channels:2
  • Temp. Range Min.(C°):-40
  • Temp. Range Max.(C°):125
  • Operation Voltage Min.(V):2
  • Operation Voltage Max.(V):3.6
  • Pin Count:48
  • Low Power:Yes
  • Number of Comparators:3
  • ADC Modules:1
  • ADC Channels:14
  • ADC Resolution Max:12
  • ADC Sampling Rate (ksps):400
  • Number of DACs:0
  • DAC outputs:0
  • Max DAC Resolution (bits):0
  • Hardware RTCC:Yes
  • Motor Control PWM Channels:0
  • SMPS PWM Channels:0
  • Number of PWM Time Bases:5
  • Output Compare Channels:5
  • USB Interface:None
  • Number of CAN Modules:0
  • Type of CAN module Max:None
  • Crypto Engine:No
  • Quadrature Encoder Interface (QEI):0
  • Segment LCD:0
  • LCD/Graphics Interface:No
  • Configurable Logic Cell Modules (CLC /CCL):4
  • Peripheral Pin Select (PPS)/Pin Muxing:Yes
  • Supported in MPLAB Code Configurator:Yes
Read more
    Core and Operating Conditions
  • 2.0V to 3.6V, -40°C to 125°C, up to 16 MIPS operation
  • Single-cycle instruction execution
  • 16 x 16 Hardware Multiply, and 32-bit x 16-bit Hardware Divider
  • C compiler optimized instruction set system
  • AEC Q100 Grade 1 qualification
    eXtreme Low Power
  • Ultra-low-power operation with sleep current down to nA with full RAM retention
  • A range of power-saving modes to reduce current consumption, while balancing performance: PMD bits, DOZE, Idle, Sleep and Retention Sleep modes
  • A range of Core Independent Peripherals (CIPs) that operate in power saving modes, while off-loading the Central Processing Unit (CPU)
    Secure Protection Features
  • Flash ‘One Time Programming’ (OTP) by ICSP™ Write Inhibit that offers an ability to disable Flash erase/write/debug operations
  • CodeGuard™ Flash protection to manage memory partitions and access restrictions
  • 120-bit Unique Device ID, 256 bytes User OTP and the above protection schemes make an ideal combination of complementary features to implement security together with the CryptoAuthentication™ devices in a secure application
    Hardware Safety Features
  • Flash with Error Correction Code (ECC) and Fault Injection for memory integrity check (Single error correction and Double error detection)
  • Dead-Man Timer (DMT) clocked by instruction fetches for monitoring the health of software
  • Windowed WatchDog Timer (WWDT) for system supervision
  • CodeGuard™ Flash protection for memory partition and access restriction
  • Fail-Safe Clock Monitor (FSCM) for clock fault management
  • Enhanced Programmable Cyclic Redundancy Check (CRC), Programmable High-Low Voltage Detect (HLVD), Brown-out Reset (BOR) and Power-on Reset (POR)
  • Class B Safety Library, IEC 60730
    Advanced Integrated Analog
  • Up to 14-Channel, 400Ksps, 10/12-Bit Analog-to-Digital Converter (ADC)
  • Low-voltage boost for input
  • Bandgap reference input feature
  • Core Independent windowed threshold compare feature
  • Auto-scan feature
  • Operation in power-saving modes
  • Three Analog Comparators with input multiplexing and programmable reference voltage generators
    Timer/Counters/Output Compare/Input Capture/Pulse Width Modulation
  • 3x 16-bit or 1x 32-bit dedicated timer/counters
  • 10x PWM or Output Compare (OC) outputs with 5 independent timer bases – Multiple Capture Compare PWMs (MCCPs)
  • 5x Input Captures (IC) – Multiple Capture Compare PWMs (MCCPs)
  • A total of 13x 16-bit or 3x 32-bit timer/counters
  • Hardware Real-Time Clock Calendar (RTCC) with Timestamping
    Core Independent Peripherals
  • 4x Configurable Logic Cells (CLCs)
  • 5x Multiple Capture Compare PWMs (MCCPs)
  • ADC controller with threshold compare and automatic triggers
  • Direct Memory Access (DMA) with 2 channels, supporting UART, SPI, ADC, and more
    Communication Interfaces
  • 2x UARTs supporting LIN/J2602 and IrDA®
  • 2x SPI/I2S, up to 25 MHz operation
  • 2x I2C Master and Slave w/Address Masking, PMBus™ and IPMI support
    Clock Management
  • On-chip 8 MHz Fast RC (FRC), and 32 kHz Low-Power RC (LPRC) and Secondary (SOSC) oscillators
  • Programmable PLL with external oscillator clock sources and Reference Clock Output (REFO)
  • Fail-Safe Clock Monitor (FSCM)
  • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) supporting two-speed start-up
    Special Features and Debugger Development Support
  • MPLAB Code Configurator (MCC) support
  • Peripheral Pin Select (PPS) for flexible pin mapping
  • Configurable interrupt-on change on all IOs
  • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2-pins
  • JTAG Boundary Scan Support
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