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Overview
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(4)
- LogicElements(K):300
- Math Blocks 18x18:924
- Fabric uPROM Kbit (kilobit):459
- Total RAM Kbit (kilobit):20600
- PCIe Lanes:2
- SERDES_Speed Gbps (gigabits per second):12.7
- SERDES lanes:16
- PLLs:8
- Temp Min °C (degrees Celsius):-40
- Temp Max °C (degrees Celsius):100
- Max. User I/O:512
- 300K logic elements
- 924 Math blocks (18x18 MACC)
- Total RAM 20.6 Mbits
- uPROM 459 Kbits
- DLL/PLL 8 each
- 16 SERDES lanes
- 2 PCIe Endpoints / Root ports
- 512 User I/O
PolarFire
FPGAs deliver the industry’s lowest power at mid-range
densities with exceptional security and reliability. Features
12.7G transceivers and offers up to 50% lower power than competing mid-range
FPGAs. The devices are ideal for a wide range of applications within wireline
access networks and cellular infrastructure, defense and commercial aviation
markets, as well as industrial automation and IoT markets.
Lower Power "L" Devices
• Provide up to 35 percent lower static power with identical electrical specifications
Data Security
• High-speed DPA safe cryptographic protocols
• Integrated true random number generator for enabling modern cryptographic protocols
• 189 MHz Athena TeraFire 5200B DPA safe Crypto Coprocessor
• NIST-certified protocols
Cost-optimized Architecture
• Transceiver performance optimized for 12.7 Gbps, which yields smaller size
• 1.6 Gbps I/Os supporting DDR4/DDR3/LPDDR3, LVDS - hardened I/O gearing logic with CDR (supports SGMII/GbE links on GPIOs)
• Best-in-class high-performance, hardened security IP in mid-range devices
Power Optimization
• The lowest static power—1/10 static power vs. competing devices
• Transceiver optimized for 12.7 Gbps, which yields 1/2 the power vs. competing devices
• Integrated hard IP—DDR PHY, PCIe endpoint/root port, crypto processor
• Total power (static and dynamic)—up to 50% lower power
Lower Power "L" Devices
• Provide up to 35 percent lower static power with identical electrical specifications
Data Security
• High-speed DPA safe cryptographic protocols
• Integrated true random number generator for enabling modern cryptographic protocols
• 189 MHz Athena TeraFire 5200B DPA safe Crypto Coprocessor
• NIST-certified protocols
Cost-optimized Architecture
• Transceiver performance optimized for 12.7 Gbps, which yields smaller size
• 1.6 Gbps I/Os supporting DDR4/DDR3/LPDDR3, LVDS - hardened I/O gearing logic with CDR (supports SGMII/GbE links on GPIOs)
• Best-in-class high-performance, hardened security IP in mid-range devices
Power Optimization
• The lowest static power—1/10 static power vs. competing devices
• Transceiver optimized for 12.7 Gbps, which yields 1/2 the power vs. competing devices
• Integrated hard IP—DDR PHY, PCIe endpoint/root port, crypto processor
• Total power (static and dynamic)—up to 50% lower power
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Tools And Software
Development Environment
Emulator and Debuggers
Demo & Evaluation Boards
Programmers
| Tools |
|---|
 Our comprehensive, easy-to-learn and easy-to-adopt development tools allow you to design with our power-efficient FPGAs.
|
| Utilize the comprehensive ecosystem of design resources for PolarFire, RTG4, IGLOO 2 and SmartFusion 2 FPGA-based designs.
|
| Start designing your embedded system today with our comprehensive design suite for our FPGAs, SoC FPGAs and radiation-tolerant FPGAs.
|
| Tools |
|---|
| FlashPro5 offers high performance through USB 2.0 that supports Serial Peripheral Interconnect (SPI) and JTAG interfaces.
|
| FlashPro6 offers exceptionally high performance through USB 3.0 that supports Serial Peripheral Interconnect (SPI) client and JTAG interfaces.
|
| Tools |
|---|
| Microchip's PolarFire Evaluation Kit offers high-performance evaluation across a broad class of applications. This kit is ideally suited for high-speed transceiver evaluation, 10Gb Ethernet, IEEE1588, JESD204B, SyncE, CPRI, and more. The kit connections include a high pin count (HPC) FPGA mezzanine card (FMC), numerous SMAs, PCIe, dual Gigabit Ethernet RJ45, SFP+, and USB. A 300K logic element (LE) PolarFire FPGA with DDR4, DDR3, and SPI-flash allow a broad class of high-performance designs to be developed.
|
| The PCIe root port adapter is a hardware evaluation platform for evaluating and testing PolarFire® FPGA PCIe root port capabilities, like the enumeration of an endpoint device and, low-speed and high-speed data transfers.
|
| The M100PF SoM family spans from 100K logic elements (LEs) to 300K LEs, features 12.7G transceivers and offers up to 50% lower power than competing mid-range FPGAs.
|
| Tools |
|---|
| FlashPro5 offers high performance through USB 2.0 that supports Serial Peripheral Interconnect (SPI) and JTAG interfaces.
|
| FlashPro6 offers exceptionally high performance through USB 3.0 that supports Serial Peripheral Interconnect (SPI) client and JTAG interfaces.
|
["developmentenvironment","Development Environment"] ,
["emulators","Emulator and Debuggers"] ,
["demoevaluationboards","Demo & Evaluation Boards"] ,
["programmerrelations","Programmers"] ,
["thirdpartytools","3rd Party Tools"] ,
["legacy","Legacy"] ,
["softwarelibraries","Library and Firmware"]
referencedesigns,Reference Designs:
codeexamples,Code Examples:
ibisboarddesignfiles,Board Design Files: