KSZ8567 | Microchip Technology

Overview

  • Copper Support:10/100 (5)
  • DownstreamPorts:5
  • Port Speed:10/100Mbps
  • Fiber Support:SGMII
  • Flow Control:Yes
  • IEEE 1588:Yes
  • IPV6:Yes
  • InterfaceUpStream:MII/RMII/RGMII/SGMII
  • InternalLDO:No
  • LinkMDCableDiag:Yes
  • Managed:Yes
  • OpVoltage:3.3
  • Rapid Spanning Tree Protocol:Yes
  • Rate Limiting:Yes
  • Smart Powe Adjust:Yes
  • Static MAC Address:Yes
  • Supply Voltages:3.3
  • Temperature Range Max:105
  • Temperature Range Min:-40
  • Digital I/O Voltage:1.8/2.5/3.3
  • WakeonLAN:Yes
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  • Non-blocking wire-speed Ethernet switching fabric
  • IEEE802.1AS (AVB) time synchronization support
  • IEEE802.1Qav (AVB) credit based traffic shaper
  • Time aware traffic scheduler with low latency cut- through mode
  • IEEE1588v2 Precision Time Protocol support
  • Time-stamping on all ports
  • Precision GPIO pin timed to the AVB/1588 clock
  • Full-featured forwarding and filtering control, including Access Control List (ACL) filtering
  • IEEE802.1X support (Port-Based Network Access Control)
  • IEEE802.1Q VLAN supportfor 128 active VLAN groups and the full range of 4096 VLAN IDs
  • IEEE802.1p/Q tag insertion or removal on a per port basis and support for double-tagging
  • VLAN ID tag/untag options on per port basis
  • IEEE802.3x full-duplex flow control and half-duplex back pressure collision control
  • IGMPv1/v2/v3 snooping for multicast packet filtering
  • IPv6 multicast listener discovery (MLD) snooping
  • QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per-port basis on four priority levels
  • IPv4/IPv6 QoS support
  • Programmable rate limiting at ingress and egress ports
  • Broadcast storm protection
  • Four priority queues with dynamic packet mapping for IEEE802.1p, IPv4 DIFFSERV, IPv6 TrafficClass
  • MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets
  • Self-address filtering for implementing ring topologies
  • High-speed SPI (4-wire, up to 50MHz) interface to access all internal registers
  • I2C Interface to access all registers
  • MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
  • In-band management to access all registers via any of the seven ports, strap enabled
  • I/O pin strapping facility to set certain register bits from I/O pins at reset time
  • Control registers configurable on-the-fly
  • Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII/RMII
  • MIB counters for fully-compliant statistics gathering (34 MIB counters per port)
  • Full-chip software power-down
  • Energy detect power-down (EDPD)
  • Support IEEE P802.3az Energy Efficient Ethernet (EEE)
  • Wake on LAN (WoL) support
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