Videos | DSPIC33CK512MPT608 | Microchip Technology

Overview

  • ADC Resolution b (bits):12
  • ADC Sampling Rate (ksps):3500
  • ADC Modules Min MB megabyte MB (megabyte):5
  • CAN/CAN-FD:2
  • Type of CAN module:CAN-FD
  • Configurable Logic Cell (CLC/CCL):4
  • CPU:dsPIC® DSC
  • CPU Speed (MIPS/DMIPS):100
  • Number of Comparators:6
  • DAC Resolution (Bits):12
  • DAC Outputs:1
  • Number of DACs:6
  • Hardware RTCC/RTC:No
  • Supported in MPLAB Code Configurator:Yes
  • Number of PWM Time Bases:15
  • Operation Voltage Max.(V):3.6
  • Operation Voltage Min.(V):3
  • Output Compare Channels:20
  • SMPS:12
  • Segmented LCD (# of segments):0
  • USB:None
  • Program Memory size (KB):512
  • Peripheral Pin Select / Pin Muxing:Yes
  • Direct Memory Access (DMA) Channels:8
  • Multiple Flash Panels:1
  • Graphics Controller/GPU:No
  • Motor Control PWM Outputs:12
  • Quadrature Encoder Interface:3
  • Low Power:No
  • ADC Channels:24
  • Pincount:100
  • Crypto Engine:Yes
  • TempRange Min:-40
  • TempRange Max:125
Read more
    Operating Conditions
  • -40ºC to +125ºC, DC to 100 MHz
  • 3.0 V to 3.6 V
  • AEC Q100 Grade 1 qualified
    dsPIC33CK DSC Core
  • Up to 512 KBytes of Program Flash with ECC and Live Update (dual-partition Flash)
  • Up to 64 KBytes of Data SRAM with Memory Built in Self-Test (MBIST)
  • Code efficient (C and Assembly) CPU architecture designed for real-time applications
  • 4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
  • Single-cycle, mixed-sign 32-bit MUL
  • Fast 6-cycle hardware 32/16 and 16/16 DIV
  • Dual 40-bit fixed point Accumulators (ACC) for DSP operations
  • Single-cycle MAC/MPY with dual data fetch and result write-back
  • Zero overhead looping support
    Security Features
  • Integrated secure subsystem with isolation as per the HSM security architecture
  • EVITA Full compliant secure subsystem
  • Secure key storage
  • Secure Subsystem with Advanced Crypto Engine (ACE) for execution of various cryptography commands
  • Fast Crypto Engine for SHA-256, HMAC and AES-CMAC algorithms
  • Sign/verify support using ECDSA – P224, P256, P384 and 256-bit Brainpool elliptic curves
  • Sign/verify support using ECDSA – SECP256K1 (bitcoin/blockchain) curve
  • RSA 2048-bit signature generation and verification
  • RSA 3072-bit signature verification only
  • Elliptic Curve Diffie-Hellman (ECDH) key agreement support for P224, P256, P384 and 256-bit Brainpool
  • Elliptic Curve Burmeiseter-Desmedt (ECBD) key agreement support for P224 curve
  • Internal symmetric and asymmetric key generation and derivation: P224, P256, P384 and 256-bit Brainpool; 2048-bit RSA keys; AES 16-byte keys
  • AES encryption/decryption supporting AES ECB/GCM modes
  • RSA 1024-bit and 2048-bit keys encryption/decryption support
  • NIST SP800-90 A/B/C Random Number Generator (RNG)
  • 16 MHz SPI interface to communicate security commands between the dsPIC core and the Secure Subsystem
  • Secure Subsystem’s authorization sessions can be used to prevent various kinds of attacks or denial of service
  • Secure Subsystem’s Advanced Crypto Engine algorithms have achieved JIL HIGH rating and are certified by FIPS as per Cryptographic Algorithm Validation Program (CAVP)
  • Secure Subsystem with FIPS 140-2 Level 2 with Physical Security Level 3 certification as per Cryptographic Module Validation Program (CMVP) [in progress]
  • CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
  • Flash configurable as One-Time Programmable (OTP) memory via ICSP Write Inhibit
  • Restricts ICSP programming/erasing operation on entire Flash memory when Flash OTP by Write Inhibit is activated using an external programmer/debugger
  • Does not allow execution from RAM
  • Support for disabling entry into debug mode
  • Support for secure provisioning
    Secure Use Cases Support
  • Immutable secure boot – Code authentication
  • Secure bootloader
  • Secure communication
  • CAN message authentication
  • WPC 1.3 Qi high-power wireless charger authentication
  • Authentication and Session Establishment
  • X.509 Certificate Validation and Storage
  • IP Protection
  • Firmware attestation
  • Device authentication OCP-SPDM specification support
    AUTOSAR-Ready DSC supporting
  • AUTOSAR (4.3.x) and ASIL B- and ASPICE-compliant MCAL drivers
  • ISO 26262 Functional Safety and Automotive Security
    High-Speed PWM Module
  • 6 independent PWM pairs (12 total outputs) with up to 250ps resolution
  • Dead-time insertion for rising and falling edges and dead-time compensation support
  • Clock chopping for high-frequency operation
  • Fault and current limit inputs
  • Flexible trigger configuration for ADC triggering
    Advanced Analog features
  • 5x 12-bit 3.5 MSPS ADC Modules each with 4 dedicated SARs and 1 shared SAR cores (5 S&Hs), 24 ADC input channels
  • 4 digital comparators and 4 oversampling filters up to 256x for increased resolution (up to 16-bits)
  • 6 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
  • Up to 3 op amps with internal connection to ADC Module
  • 2 Current Bias Generators (CBGs)
    Timer/Counters/Output Compare/Input Capture
  • 21 16-bit timer/counters (up to 12 32-bit)
  • 12 PWM or Output Compare (OC) outputs
  • 9 Input Captures (IC) pins or internal connections from the CLC or Comparator Modules
  • 3 Quadrature Encoder Interface (QEI) Modules for optical encoder support
  • Peripheral Trigger Generator (PTG) for scheduling complex sequences
    Communication Interfaces
  • 3 UARTs (15 Mbps) with automated protocol handling for LIN/J2602, DMX and IrDA®
  • 3x 4-wire SPI/I2S up to 40 MHz with dedicated pins
  • 3 I2C Modules (up to 1 Mbps) with SMBus support
  • 2 CAN Flexible Data Rate (CAN-FD) Module ("50x devices only)
  • 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
  • 8 DMA channels supporting UART, SPI, ADC, CAN-FD, IC, OC and Timer data transfers
    Special Features
  • 4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
  • Programmable Pin Select (PPS) for peripheral pin function mapping
  • On-chip temperature sensor with direct ADC Module connection
    Functional Safety Features
  • Dead-Man Timer (DMT) and Watch Dog Timer (WDT)
  • CodeGuard™ security for program FLASH
  • Programmable Cyclic Redundancy Check (CRC)
  • FLASH ECC Fault Injection testing feature
  • RAM Memory Built-In Self Test (MBIST)
  • Fail-Safe Clock Monitoring (FSCM) with redundant clock sources
  • Capless Internal Voltage Regulator
  • Virtual Pins for Redundancy and Monitoring
  • I/O Port read-back
  • Analog peripherals redundancies and more
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