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In Production
Summary

The LAN8650 combines a Media Access Controller (MAC) and an Ethernet PHY to enable low‑cost microcontrollers, including those without an onboard MAC, to access 10BASE‑T1S networks. The common standard Serial Peripheral Interface (SPI) of the LAN8650 allows interfacing with nearly any microcontroller, so that the transfer of Ethernet packets and LAN8650 control/status commands are performed over a single, serial interface. SPI also requires only 4 pins, enabling a simpler hardware interface with fewer pins than MII or RMII.

Microchip's complimentary and confidential MicroCHECK design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.

The LAN8650 is designed to be used in ISO 26262 Functional Safety applications. A Functional Safety Package is available, including Safety Manual; Failure Modes, Effects, and Diagnostic Analysis (FMEDA); and Dependent Failure Analysis (DFA). For additional information please contact Microchip Support or Sales.

Available from MikroElektronika, featuring the LAN8651, is the TWO-WIRE ETH CLICK - MIKROE-5543, a compact add-on board with the purpose of a generic interface to many microcontrollers in 10BASE-T1S applications.

The LAN8651 combines a Media Access Controller (MAC) and an Ethernet PHY to enable low‑cost microcontrollers, including those without an onboard MAC, to access 10BASE‑T1S networks. The common standard Serial Peripheral Interface (SPI) of the LAN8651 allows interfacing with nearly any microcontroller, so that the transfer of Ethernet packets and LAN8651 control/status commands are performed over a single, serial interface. SPI also requires only 4 pins, enabling a simpler hardware interface with fewer pins than MII or RMII.

Microchip's complimentary and confidential MicroCHECK design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.

The LAN8651 is designed to be used in ISO 26262 Functional Safety applications. A Functional Safety Package is available, including Safety Manual; Failure Modes, Effects, and Diagnostic Analysis (FMEDA); and Dependent Failure Analysis (DFA). For additional information please contact Microchip Support or Sales.

Features
    High-performance 10BASE‑T1S single-pair Ethernet PHY designed to IEEE Std. 802.3cg™-2019
  • 10 Mbit/s over a single balanced pair
  • Half-duplex multidrop mixing segments up to at least 25m with up to at least 8 PHYs
  • Half-duplex point-to-point link segments up to at least 15m
    Physical Layer Collision Avoidance (PLCA)
  • Burst mode for transmission of multiple packets for latency-sensitive applications
  • Minimize latency for time-sensitive applications by assigning multiple PLCA IDs per node
    Carrier Sense Multiple Access / Collision Detection (CSMA/CD) media access control
    Application Controlled Media Access (ACMA) for implementation of collision-free Time-Division Multiple Access (TDMA) methods
    Integrated Media Access Controller (MAC)
    Industry standard Serial Peripheral Interface (SPI), designed to the OPEN Alliance 10BASE T1x MAC PHY Serial Interface specification, V1.1
    Support for Time Sensitive Networks (IEEE Std 802.1AS™ / IEEE 1588™)
  • Internal wall clock
  • Event generation and event capture synchronized to the wall clock
  • Phase adjuster for the wall clock to minimize microcontroller overhead
  • Packet timestamping
    Credit-based traffic shaping
    EtherGREEN™ Energy Efficiency
  • Ultra-low power sleep mode
  • Wake up triggered by either MDI activity or local WAKE_IN
  • WAKE_OUT pulse assertion; INH output for enable/disable of ECU supply
    Over-temperature and under-voltage protection
    Cable fault diagnostics and Signal Quality Indication (SQI) support
    Enhanced electromagnetic compatibility / electromagnetic interference (EMC/EMI) performance
    Small footprint 32-pin (5 x 5 mm) VQFN package with wettable flanks
    -40°C to +125°C extended temperature range
    AEC-Q100 qualification
    Functional Safety Support: Functional Safety Manual, FMEDA, Dependent Failure Analysis (DFA)
    AUTOSAR MCAL evaluation package available
  • Developed as per AUTOSAR version R21-11
  • Sample application available to assist configuration of peripherals
  • Easy to integrate into any host microcontroller’s AUTOSAR stack
  • Supports multiple MAC-PHY connected to same microcontroller
    High-performance 10BASE‑T1S single-pair Ethernet PHY designed to IEEE Std. 802.3cg™-2019
  • 10 Mbit/s over a single balanced pair
  • Half-duplex multidrop mixing segments up to at least 25m with up to at least 8 PHYs
  • Half-duplex point-to-point link segments up to at least 15m
    Physical Layer Collision Avoidance (PLCA)
  • Burst mode for transmission of multiple packets for latency-sensitive applications
  • Minimize latency for time-sensitive applications by assigning multiple PLCA IDs per node
    Carrier Sense Multiple Access / Collision Detection (CSMA/CD) media access control
    Application Controlled Media Access (ACMA) for implementation of collision-free Time-Division Multiple Access (TDMA) methods
    Integrated Media Access Controller (MAC)
    Industry standard Serial Peripheral Interface (SPI), designed to the OPEN Alliance 10BASE T1x MAC PHY Serial Interface specification, V1.1
    Support for Time Sensitive Networks (IEEE Std 802.1AS™ / IEEE 1588™)
  • Internal wall clock
  • Event generation and event capture synchronized to the wall clock
  • Phase adjuster for the wall clock to minimize microcontroller overhead
  • Packet timestamping
    Credit-based traffic shaping
    EtherGREEN™ Energy Efficiency
  • Ultra-low power sleep mode
  • Wake up triggered by either MDI activity or local WAKE_IN
  • WAKE_OUT pulse assertion; INH output for enable/disable of ECU supply
    Over-temperature and under-voltage protection
    Cable fault diagnostics and Signal Quality Indication (SQI) support
    Enhanced electromagnetic compatibility / electromagnetic interference (EMC/EMI) performance
    Small footprint 32-pin (5 x 5 mm) VQFN package with wettable flanks
    -40°C to +125°C extended temperature range
    AEC-Q100 qualification
    Functional Safety Support: Functional Safety Manual, FMEDA, Dependent Failure Analysis (DFA)
    AUTOSAR MCAL evaluation package available
  • Developed as per AUTOSAR version R21-11
  • Sample application available to assist configuration of peripherals
  • Easy to integrate into any host microcontroller’s AUTOSAR stack
  • Supports multiple MAC-PHY connected to same microcontroller