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IGLOO2_3XOVERSAMPLING

Title	Title IGLOO2 High Speed SERDES 3x Oversampling Design User Guide
Name	Name IGLOO2_3XOVERSAMPLING
Date	Date 06/24/2020
Description	Description IGLOO®2 field programmable gate array (FPGA) devices have embedded high speed serial/deserializer (SERDES) blocks that can handle data rates from 1 Gbps to 5 Gbps. Because of internal phase locked loop (PLL) operating range limitations, the lower cutoff data rate of the high speed SERDES block is 1000 Mbps.

Files

Title	Title	Download	Date	Size
IGLOO2 High Speed SERDES 3x Oversampling 120.5 MB 10/28/2022	IGLOO2 High Speed SERDES 3x Oversampling	Download	10/28/2022	120.5 MB

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