Title |
Title
AN_2717 - SAMA5D2 Dynamic Memory Implementation Guidelines
|
---|---|
Name |
Name
AN2717-2
|
Date |
Date
11/15/2018
|
Description |
Description
Design recommendations for SAMA5D2 series microprocessors regarding PCB layout and software settings to ensure proper device functionality with multiple SDRAM device types
|
Title | Product | Title |
---|---|---|
ATSAMA5D28C-LD2G
A high-performance, low-power Arm Cortex-A5 CPU-based embedded microprocessor (MPU) running up to 500 MHz, with 2Gbit LPDDR2 memory.
|
ATSAMA5D28C-LD2G | A high-performance, low-power Arm Cortex-A5 CPU-based embedded microprocessor (MPU) running up to 500 MHz, with 2Gbit LPDDR2 memory. |
ATSAMA5D43
Cortex-A5 based Microprocessor
|
ATSAMA5D43 | Cortex-A5 based Microprocessor |
ATSAMA5D44
Cortex A5 based MPU w/ LCD and Video Decoder
|
ATSAMA5D44 | Cortex A5 based MPU w/ LCD and Video Decoder |
ATSAMA5D42
Cortex-A5 based Microprocessor
|
ATSAMA5D42 | Cortex-A5 based Microprocessor |
ATSAMA5D41
A high-performance, ultra-low-power ARM Cortex-A5 processor-based MPU.
|
ATSAMA5D41 | A high-performance, ultra-low-power ARM Cortex-A5 processor-based MPU. |