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AC450
| Title |
Title
Timing Optimization for AXI3 DDR Interfaces Using SmartFusion2/IGLOO2 - Application Note
|
|---|---|
| Name |
Name
AC450
|
| Date |
Date
06/16/2021
|
| Application Categories |
Application Categories
General Purpose
|
| Description |
Description
This application note describes the optimization techniques used for meeting timing closure on SmartFusion®2 and IGLOO®2 designs that use non-1:1 Double Data Rate (DDR) to Advanced eXtensible Interface (AXI) clock ratios (2:1, 3:1, and 4:1). It provides reference designs for the SmartFusion2 Advanced Development Kit board and IGLOO2 Evaluation Kit board.
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Files
| Title | Title | Download | Date | Size |
|---|---|---|---|---|
| m2s_m2gl_ac450_df.zip 885.8 MB 11/17/2021 | m2s_m2gl_ac450_df.zip | Download | 11/17/2021 | 885.8 MB |
Silicon Products
| Title | Product | Title |
|---|---|---|
|
M2GL010
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M2GL010 | More Resources in Low Density Devices |
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M2GL025
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M2GL025 | More Resources in Low Density Devices |
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M2GL050
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M2GL050 | More Resources in Low Density Devices |
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M2GL060
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M2GL090
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M2GL090 | More Resources in Low Density Devices |
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M2GL150
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M2GL150 | More Resources in Low Density Devices |
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M2GL005
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M2GL005 | More Resources in Low Density Devices |