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AC428

Title	Title SmartFusion2 and IGLOO2 - DDR Low Power Modes - Libero SoC v11.7 Application Note
Name	Name AC428
Date	Date 02/17/2016
Application Categories	Application Categories General Purpose
Description	Description This application note describes the double-data rate (DDR) low power modes using an example design for the IGLOO®2 field programmable gate array (FPGA) Evaluation Kit board. The DDR low power modes explained in this application note can also be used for the SmartFusion®2 system-on-chip (SoC) FPGA devices.

Files

Title	Title	Download	Date	Size
m2s_m2gl_ac428_ddrlowpwr_liberov11p7_df.zip 27.9 MB 11/17/2021	m2s_m2gl_ac428_ddrlowpwr_liberov11p7_df.zip	Download	11/17/2021	27.9 MB

Title	Product	Title
M2GL010 More Resources in Low Density Devices	M2GL010	More Resources in Low Density Devices
M2GL025 More Resources in Low Density Devices	M2GL025	More Resources in Low Density Devices
M2GL050 More Resources in Low Density Devices	M2GL050	More Resources in Low Density Devices
M2GL060 More Resources in Low Density Devices	M2GL060	More Resources in Low Density Devices
M2GL090 More Resources in Low Density Devices	M2GL090	More Resources in Low Density Devices
M2GL150 More Resources in Low Density Devices	M2GL150	More Resources in Low Density Devices
M2GL005 More Resources in Low Density Devices	M2GL005	More Resources in Low Density Devices