dsPIC33CH128MP503 | Microchip Technology

Overview

  • CPU Type:dsPIC® DSC
  • CPU Speed Max MHz (megahertz):100
  • Program Memory Size (KB):128
  • Multiple Flash Panels:False
  • Direct Memory Access (DMA) Channels:8
  • Temp. Range Min.(C°):-40
  • Temp. Range Max.(C°):150
  • Operation Voltage Min.(V):3
  • Operation Voltage Max.(V):3.6
  • Pin Count:36
  • Low Power:No
  • Number of Comparators:4
  • ADC Modules:4
  • ADC Channels:17
  • ADC Resolution Max:12
  • ADC Sampling Rate (ksps):3500
  • Number of DACs:4
  • DAC outputs:1
  • Max DAC Resolution (bits):12
  • Hardware RTCC:No
  • Motor Control PWM Channels:12
  • SMPS PWM Channels:12
  • Number of PWM Time Bases:5
  • Output Compare Channels:0
  • USB Interface:None
  • Number of CAN Modules:1
  • Type of CAN module Max:CAN-FD
  • Crypto Engine:No
  • Quadrature Encoder Interface (QEI):1
  • Segment LCD:0
  • LCD/Graphics Interface:No
  • Configurable Logic Cell Modules (CLC /CCL):8
  • Peripheral Pin Select (PPS)/Pin Muxing:Yes
  • Supported in MPLAB Code Configurator:Yes
Read more
    Operating Conditions
  • 3V to 3.6V, -40°C to +150°C
    Core: Dual Core dsPIC33CH DSCs
  • Main Core 90 MHz and Secondary Core 100 MHz Operation
  • Independent Peripherals for Main Core and Secondary Core
  • Configurable Shared Resources for Main Core and Secondary Core
  • Fast 6-Cycle Divide
  • Message Boxes and FIFO to Communicate Between Main and Secondary (MSI)
  • Code Efficient (C and Assembly) Architecture
  • 40-Bit Wide Accumulators
  • Single-Cycle (MAC/MPY) with Dual Data Fetch
  • Single-Cycle, Mixed-Sign MUL Plus Hardware Divide
  • 32-Bit Multiply Support
  • Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
  • Zero Overhead Looping
    High Performance Peripherals for Real Time Control
  • 4 x 12-bit 3.5 MSPS ADCs
  • High Speed PWMs with 250ps resolution, 12 Ch
  • Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
    Main Core features
  • Core Frequency: 90 MHz
  • Internal Data RAM: 16 Kbytes
  • 16-Bit Timer: 1
  • DMA: 6
  • SCCP (Capture/Compare/Timer): 8
  • UART: 2
  • SPI/I2S: 2
  • I2C: 2
  • CAN Flexible Data-Rate (FD): 1
  • SENT: 2
  • CRC: 1
  • QEI: 1
  • PTG:1
  • CLC: 4
  • 16-Bit High-Speed (250ps) PWM: 4
  • 12-bit, 3.5 Msps ADC: 1
  • Digital Comparator: 4
  • 12-Bit DAC/Analog CMP Module: 1
  • Watchdog Timer: 1
  • Deadman Timer: 1
  • Breakpoints: 3 complex, 5 simple
  • Oscillator: 1
    Secondary Core features
  • Core Frequency: 100 MHz
  • Program Memory: 24 Kbytes (PRAM) Dual Partition with LiveUpdate
  • Internal Data RAM: 4 Kbytes
  • 16-Bit Timer: 1
  • DMA: 2
  • SCCP (Capture/Compare/Timer): 4
  • UART: 1
  • SPI/I2S: 1
  • I2C: 1
  • QEI: 1
  • CLC: 4
  • 16-Bit High-Speed (250ps) PWM: 8
  • 12-bit, 3.5 Msps ADC: 3
  • Digital Comparator: 4
  • 12-Bit DAC/Analog CMP Module: 3
  • Watchdog Timer: 1
  • Breakpoints: 1 complex, 2 simple
  • Oscillator: 1
    Clock Management
  • Internal Oscillator
  • Programmable PLLs and Oscillator Clock Sources
  • Main Reference Clock Output
  • Secondary Reference Clock Output
  • Fail-Safe Clock Monitor (FSCM)
  • Fast Wake-up and Start-up
  • Backup Internal Oscillator
  • LPRC Oscillator
    Power Management
  • Low-Power Management Modes (Sleep, Idle, Doze)
  • Integrated Power-on Reset and Brown-out Reset
    Debugger Development Support
  • In-Circuit and In-Application Programming
  • Simultaneous Debugging Support for Main and Secondary Cores
  • Main Only Debug and Secondary Only Debug Support
  • IEEE 1149.2 Compatible (JTAG) Boundary Scan
  • Trace Buffer and Run-Time Watch
    Core Independent Touch
  • Uses Peripheral Trigger Generator (PTG) and High-speed ADCs
  • Ready-to-use touch library support in MPLAB Code Configurator (MCC)
    Embedded Security
  • CodeGuard security together with Flash OTP by ICSP Write Inhibit enables implementing Immutable Secure Boot
  • Flash OTP by ICSP Write Inhibit to configure entire Flash as OTP
  • Option to disable entry to the debug mode
  • User OTP
  • Enables implementing robust security use cases together with CryptoAuthentication and CryptoAutomotive devices such as:
  • Secure Boot
  • Secure Firmware Upgrade
  • Secure Communication
  • Node Authentication and more
    Functional Safety hardware features
  • Dead-Man Timer (DMT) safety feature clocked by instruction fetches
  • Watch Dog Timer (WDT)
  • CodeGuard™ security for program FLASH
  • Programmable Cyclic Redundancy Check (CRC)
  • FLASH ECC Fault Injection testing feature
  • Flash OTP by ICSP™ write inhibit
  • Class B Safety Library, IEC 60730
  • RAM Memory Built-In Self Test (MBIST)
  • Two-Speed Start-up
  • Fail-Safe Clock Monitoring (FSCM)
  • Backup FRC (BFRC)
  • Capless Internal Voltage Regulator
  • Virtual Pins for Redundancy and Monitoring
  • Multiple redundant clock sources
  • I/O Port read-back
  • Analog peripherals redundancies
  • Hardware traps
  • SFR locks
  • Write protection
  • Shadow working registers
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dsPIC33CH128MP503
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