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CoreGPIO

Core GPIO provides an Advanced Peripheral Bus (APB) register-based interface to up to 32 generalpurpose inputs and 32 general purpose outputs. The input logic contains a simple three-stagesynchronization circuit, and the output is also set synchronously. Each bit can be set to either fixedconfiguration or register-based configuration through top-level parameters, including input type, interrupttype / enable, and output enable.


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Features and Benefits

  • Advanced microcontroller bus architecture (AMBA) 2 APB support, forward compatibility with AMBA3 APB
  • 8-, 16-, or 32-bit APB data width
  • 1 to 32 bits of I/O for all APB-width configurations
  • Fixed or configurable interrupt generation:
  • Parameter-configurable for single-interrupt signal or up to 32-bit wide interrupt bus
  • Fixed or configurable I/O type (input, output, or both)
  • Configurable output enable (internal or external implementation)

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    HB0183: CoreGPIO v3.2 Handbook Download