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Microchip Polarfire FPGA 3.5W, 59.8°C, 24.2 FIT, 28nm
Competitor X FPGA 6.0W, 81.3°C, 96.3 FIT, 16nm
Microchip FPGAs and SoC FPGAs consume up to 50% lower total power than competitive FPGAs. Our nonvolatile process delivers FPGA families that are live at power-up with minimal in-rush current, and significantly lower leakage than SRAM-based alternatives. Take it one step further; run a power benchmark with our power estimator.
- Fanless enclosures with small/no heat sink
- Increased thermal headroom for more compute capability
PolarFire FPGAs and PolarFire SoCs—Low Power by Design
The PolarFire family of devices is built and designed for low power. We use a proven low-power 28 nm CMOS process for wafer fabrication and we’ve designed the FPGA fabric for low static power consumption. We also use state-of-the art transceiver designs to minimize total transceiver power. The PolarFire FPGA delivers the lowest power in the smallest form factors in a mid-range FPGA to give you more compute capability within a fixed power or thermal budget.
The CoreMarks® per Watt benchmark measures the power consumption of competitive SoC FPGAs using available power estimators. The entire device is powered while only the processor subsystem is operating. It is a chip-to-chip comparison, not a CPU-to-CPU comparison. Power is measured at worst-case process and 100°C Tj.
PolarFire MPFS025 SoC Performance
MPLAB X IDE
Organize, write, test and debug your embedded software applications in the MPLAB X IDE.
MPLAB XC Compiler
Build your embedded software with the TÜV SÜD-certified MPLAB XC8 Pro Functional Safety Compiler.
MPLAB Analysis Tool Suite
MPLAB Analysis Tool Suite offers a code coverage feature and a Motor Industry Software Reliability Association (MISRA®) check in the IDE.
FPGA Design Tools
Explore our comprehensive selection of hardware and software development tools to accelerate your application development with FPGAs and SoCs.
Thermal Runaway
Thermal runaway can be a problem for SRAM FPGAs. Use power estimators to sweep the temperature to determine when a heat sink is needed for SRAM FPGAs.
Minimal In-Rush and Zero Configuration Current
SRAM FPGAs require a complex power up and reset sequencing. High in-rush currents occur during device initialization and configuration. Leveraging our SoC FPGAs simplifies sequencing requirements and components, reducing system cost, design complexity and board space.
Instant On
Our instant-on FPGAs assist in system startup tasks, system configuration and supervision. Instant-on functionality simplifies power-up sequence requirements with fewer components and lower cost while enhancing security and reducing initialization time.