On-Chip Debugging With Probe Insertion

Probe insertion is a post-layout process that allows you to insert probes into your IGLOO, ProASIC 3, SmartFusion or Fusion FPGA design and bring signals out to the FPGA package pins to evaluate and debug the design. While testing a programmed device, your design may have inherent logic errors due to inadequate simulation test coverage, external signals that arrived out of sequence or oversight of timing setup and hold violations.

Our post-layout probe insertion is faster than using Synopsys® Identify® ME, which requires instrumentation of the design at the RTL level before running synthesis, layout and device programming.

Probe insertion can select internal nets anywhere in the design, connecting the selected signals to unused pins. Nets are selected and assigned using the generate probed design feature from the designer tools menu. If all pins are already assigned, a temporary assignment can be used to override a less-important output.

Probe insertion has a minimal timing effect on the overall design and is a convenient way to quickly understand logic issues in any design. The original saved layout file is retained and the process can be used if no design modifications are needed. Alternatively, any necessary modifications can be made to the design so that layout can be run again.

Probe insertion allows you to select internal nets anywhere in the design, connect the selected signals to unused pins and run the incremental layout to manage the physical connection to the pin. Nets are selected and assigned probes using the generate probed design feature available from the designer tools menu. If all package pins are already assigned, a used pin can be temporarily disconnected to enable connection of the probed signal to that pin. You can then program the re-routed design into the FPGA where you can use an external logic analyzer or oscilloscope to view the activity of the probed signal. The package pins and port names are reported in your log file. Once the evaluation is complete, the original saved layout file can be used if no design modifications are needed, or any necessary modifications can be made to the design so that layout can be run again.

The designer probe insertion feature is available from the Libero® SoC Design Suite designer toolbar.

With FlashPro’s on-chip debug features, you can inspect specific blocks within IGLOO, ProASIC 3, SmartFusion and Fusion FPGAs via the JTAG interface. The on-chip debug features allow you to view the programmed contents of embedded Flashrom, Nonvolatile Memory (NVM) and analog blocks to determine if the data that is actually programmed into these blocks agrees with the pre-programming design parameters. This feature is helpful in the rare event of corruption between the original design file creation and device programming or for final design analysis prior to the FPGA system testing or production.

FlashPro on-chip debug reads the Flashrom data from the programmed FPGA device and automatically compares the data to the Programming Database (PDB) file generated by Libero SoC Design Suite. Any mismatch between the device data and the design file is automatically highlighted for the user in the Flashrom inspection interface window.

FlashPro on-chip debug reads the NVM content from the programmed FPGA device and displays the data. You can compare the content of the device data to the data from the PDB programming file. This read-only feature displays the programmed NVM data for each user client or for each NVM page address. It can also detect corruption on a per-page basis so that you can quickly locate the problematic areas.

On-chip debug allows you to perform multiple inquiries of the programmed SmartFusion and Fusion FPGA analog block attributes, including inspection of the analog block data on a channel-by-channel basis. The programmed FPGA device data can be compared to the analog block configurations generated by Libero SoC Design Suite. Any mismatches are highlighted.

FlashPro on-chip debug also supports viewing of device status information, such as device state, security settings and power supply voltages supplied to the FPGA.

Launch FlashPro on-chip debug with the inspect device button on the FlashPro software tool interface.