For SmartFusion® 2/IGLOO® 2 FPGA designs, only SmartFusion 2 FPGA libraries are required for simulations.
For SmartFusion FPGA designs, both SmartFusion FPGA and MSS_BFM_LIB libraries are needed for simulations.
When using Cadence NCSim libraries, pre-synthesis simulations of DDR designs simulated with DDR VIP in testbench will fail. We recommend directly running post-synthesis or post-layout simulations.
Pre-Compiled Simulation Libraries for Version 2024.2 of Libero® SoC Design Suite