For SmartFusion® 2/IGLOO® 2 FPGA designs, only SmartFusion 2 FPGA libraries are required for simulations.
For SmartFusion FPGA designs, both SmartFusion FPGA and MSS_BFM_LIB libraries are needed for simulations.
When using Cadence NCSim libraries, pre-synthesis simulations of DDR designs simulated with DDR VIP in testbench will fail. We recommend directly running post-synthesis or post-layout simulations.
Pre-Compiled Simulation Libraries for Version 2025.1 of Libero® SoC Design Suite
{"SalesForceSecurePath":"https://microchip.my.salesforce-scrt.com","EmbeddedServiceName":"Messaging_For_Microchip","SalesForcePath":"https://microchip.my.site.com/ESWMessagingForMicrochi1755319480924","AgentAvailableHeader":"No problem. Chat with our engineering experts or schedule a call that's convenient for you.","ScheduleCallUrl":"https://microchip.my.site.com/schedulemeetingportal/s/","SalesforceOrgId":"00Do0000000KAkK","JsUrl":"https://microchip.my.site.com/ESWMessagingForMicrochi1755319480924/assets/js/bootstrap.min.js"}