The Microchip DSP design flow enables the DSP designer to evaluate an algorithm at a higher level of abstraction using MATLAB® and Simulink® along with an exhaustive set of DSP blocksets and Microchip IP. The DSP designer can then follow a seamless and intuitive design flow to translate, optimize, and verify the design at RTL, gate, and physical level with this industry-leading tool set. The result is very short development time and a fast time to market.

DSP Design Flow Example

Algorithm Design -> Conversion to Fixed-Point -> RTL Generation -> Libero SoC Design Suite

Algorithm Design

Starting with a concept, a DSP architect translates ideas into a design in the MATLAB and Simulink environment. DSP blocks supplied by the FPGA or the EDA tool vendors are used at this stage. For instance, targeting the Microchip FPGA device, the architect or designer uses blocksets supplied by Synphony Model Compiler ME and/or Microchip IP.

Conversion to Fixed Point

Simulink provides an environment for simulating the design and analyzing its behavior using floating-point and fixed-point accuracies. Simulation can be performed using the built-in stimuli and scope block sets in Simulink. Floating point format provides a baseline performance of the algorithm that helps in the analysis of the fixed-point behavior of the design. 

High-Level Synthesis Optimization and RTL Generation

The DSP design can be synthesized into architecturally-optimized RTL by using Synphony Model Compiler ME, which is a high-level synthesis (HLS) tool that performs architectural optimizations from the Simulink specification. These HLS optimizations allow designers to capture the behavior needed for their algorithm without worrying about the specific implementation in hardware. Synphony Model Compiler ME performs transformations and optimizations of the DSP Simulink design based on the Microchip target device and then generates the RTL.

Synphony Model Compiler ME Optimization Strategies

• Folding: This optimization strategy helps in reducing the area utilization by reusing the same area hardware components (such as multipliers) for multiple streams of data. This results in a very compact design. This optimization is a tradeoff between the area utilization of the hardware and the higher clock rate required to maintain similar data rates.
• Retiming: Retiming optimization is similar to the register balancing optimization done at the RTL Synthesis level; in this case, though, the optimization is done at the system architecture level.
• Multi-Channelization: Once an algorithm has been developed and verified in Simulink, the design can then be replicated over multiple channels. This optimization replicates the design and then automatically applies optimizations which synthesize the time-domain multiplexer logic required for a better area.

More Synphony Model Compiler ME Features:

• Rapid algorithm design and simulation in Simulink
• Easy floating and fixed-point conversion and analysis
• Fully integrated fixed-point blockset of DSP functions
• User-customizable IP blockset
• Automatic generation of code and testbench RTL
• New system-level optimizations for improved performance and area
• VHDL and Verilog language support
• Co-simulation with ModelSim

For further information on Synphony Model Compiler, refer to the Synopsys website.
For use with Microchip devices, Synphony Model Compiler ME is installed with Libero SoC Design Suite.

Physical Implementation

The figure above shows the FPGA implementation environment where the RTL design generated from Synphony Model Compiler ME is synthesized, simulated (optional), and mapped to the FPGA device. There are several tools involved in this process; the design flow has been made easy with the flowchart shown in the tool. You push the relevant buttons in the flow to complete the tasks.