How Microchip FPGAs Can Improve Productivity in Motor Control Applications Using C++ with HLS

Introduction to Advanced Motor Control Applications

Motor control applications today demand multi-axis, multi-function solutions with bounded results. Consider a robot in a large automated industrial manufacturing unit (performing a task in a loop) or even a robot-assisted medical surgery - These robots would need precise control in all directions with deterministic outputs. Similarly, high-end industrial drones require stable gyros and improved mechanical reliability combined with the high-speed calculations capabilities of a DSP. In more critical scenarios such as a medical implant like a Ventricular Assist Device (to help a heart pump better), in addition to precision and determinism, robustness and reliability are imperative since there is no tolerance for failure. Electric Motors also perform critical functions such as attitude control, deployment mechanisms, motion and throttle valve control in space vehicles. Wing actuators maintain fuel efficiency in airplanes at lower speeds, typically after takeoff or when preparing to land. These applications necessitate long operating life, high reliability, and security, under high vacuum, radiation, and varying operating environments.

There is always a perpetual need to lower system costs – to have a single networked, multi-protocol hardware that Integrates digital peripherals with a processor core.

The FPGA Advantage in Motor Control Designs

FPGAs offer numerous advantages over ASICs, the most obvious being deterministic, parallel-computing with field re-configurability. They can implement complex logic functions supporting multiple system implementations and revisions.

Our FPGAs are unique in that they are made from non-volatile flash-based memory. This instant-on technology enables them to deliver 30 to 50 per cent lower power than competing FPGAs. They offer radiation immunity, and unique security features such as prevention of overbuilding and cloning, design IP protection, a root of trust, secure data communications and anti-tamper capabilities. Specifically, in the motor control context, our FPGAs play a big role in solving the complex challenges faced by modern-day motor control applications by offering low power, low jitter low-latency, high precision, determinism, and scalability.

SmartHLS to Boost Productivity

Designing a new hardware-based motor controller from scratch for an FPGA, using Verilog/VHDL, can be time-consuming. Typically, an engineer already has a working motor controller designed in C/C++. In this situation, the ideal solution is to automatically convert the existing C++ software code into an equivalent hardware implementation, targeting a Microchip PolarFire FPGA. This is made easy by the Smart High-Level Synthesis (SmartHLS™ ) tool and integrated development environment, which can compile C++ software into a hardware block targeting a Microchip FPGA. High-level synthesis allows you to take C++ as input and generate Verilog as output. Typically, you mark the top-level C++ function that HLS will generate into an equivalent hardware IP core. You can describe your algorithm in the top-level C++ function. Then you use HLS pragmas and C++ HLS library to describe standard hardware interfaces like AXI, AXI-stream, or memory interfaces. A compelling benefit of HLS is that it affords you a significant level of abstraction with C++ over RTL designs and enhanced productivity - for hardware design and verification time. Use HLS for architecture exploration since the tool can easily add or remove pipeline registers to achieve the user-specified target frequency.

We had a customer migrate their advanced motor control design with stringent constraints to our FPGAs using SmartHLS. Their primary goal was to achieve a deterministic latency of less than 3 us. This latency is the time for feedback between receiving each of the eight motor’s encoder sensors and the FPGA motor control core updating the current output for all of them. The customer also wanted the design to run at above 200MHz clock frequency due to external I/O requirements such as DDR and PCIe. They also wanted to fit the design on a PolarFire MPF500 device with room to spare. 

They reported their quality of results and were able to beat their design goals out of the park.  They observed a 50% reduction in cycle latency while the frequency improved to meet the 200 MHz target clock frequency. The final deterministic latency for the motor controller was also halved to approximately 2 μs. The area of the motor controller was also reduced to fit inside the 300K LE PolarFire FPGA.

Experiments comparing the original C++ motor controller to the improved FPGA version revealed that the FPGA-based motor controller had a 2.5-6x speedup in terms of latency compared to the Arm microcontroller, depending on the jitter of the microcontroller and real-time operating system.

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