Altium

Design Rule Verification Report

Date: 8/7/2020
Time: 11:08:48 AM
Elapsed Time: 00:00:03
Filename: C:\Users\m51778\Downloads\APID_HW\Solar Breaker\Solar breaker(HV9901+MCP39F511A)_V3.0_8-06-2020\Solar breaker(HV9901+MCP39F511A)_V3.0.PcbDoc
Warnings: 1
Rule Violations: 43

Summary

Warnings Count
Design contains shelved or modified (but not repoured) polygons. The result of DRC is not correct. Recommended to restore/repour all polygons and proceed with DRC again 1
Total 1

Rule Violations Count
Clearance Constraint (Gap=0.178mm) (All),(All) 6
Short-Circuit Constraint (Allowed=No) (IsNet),(All) 0
Un-Routed Net Constraint ( (All) ) 1
Un-Connected Pin Constraint ( (All) ) 17
Modified Polygon (Allow modified: No), (Allow shelved: No) 1
Width Constraint (Min=0.254mm) (Max=1.524mm) (Preferred=0.254mm) (InNet('GND')) 1
Width Constraint (Min=0.203mm) (Max=10.16mm) (Preferred=0.254mm) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=0.3mm) (MaxHoleWidth=1.6mm) (PreferredHoleWidth=0.4mm) (MinWidth=0.203mm) (MaxWidth=2.5mm) (PreferedWidth=0.8mm) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.25mm) (Max=0.254mm) (Prefered=0.254mm) and Width Constraints (Min=0.25mm) (Max=0.381mm) (Prefered=0.381mm) (All) 0
SMD To Corner (Distance=0.1mm) (All) 4
Power Plane Connect Rule(Relief Connect )(Expansion=0.3mm) (Conductor Width=0.25mm) (Air Gap=0.25mm) (Entries=4) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.5mm) (Conductor Width=0.3mm) (Air Gap=0.3mm) (Entries=4) (IsVia) 0
Minimum Annular Ring (Minimum=0.15mm) (All) 2
Acute Angle Constraint [Tracks Only] (Minimum=90.000) (All) 2
Hole Size Constraint (Min=0.25mm) (Max=6mm) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=0mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All) 0
Silk To Solder Mask (Clearance=0mm) (IsPad),(All) 0
Silk to Silk (Clearance=0.025mm) (All),(All) 0
Net Antennae (Tolerance=0.003mm) (All) 2
Board Clearance Constraint (Gap=0mm) (All) 0
Board Clearance Constraint (Gap=0mm) (OnLayer('Top Overlay','Bottom Overlay')) 7
Total 43

Warnings

Design contains shelved or modified (but not repoured) polygons. The result of DRC is not correct. Recommended to restore/repour all polygons and proceed with DRC again
Polygon named: Component Side-No Net In net GND On Component Side
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Clearance Constraint (Gap=0.178mm) (All),(All)
Clearance Constraint: (Collision < 0.178mm) Between Pad RS1-3(14.319mm,52.206mm) on Component Side And Track (14.378mm,52.143mm)(15.561mm,52.143mm) on Component Side
Clearance Constraint: (Collision < 0.178mm) Between Pad RS1-4(8.769mm,52.206mm) on Component Side And Track (7.499mm,52.206mm)(8.682mm,52.206mm) on Component Side
Clearance Constraint: (Collision < 0.178mm) Between Track (12.003mm,52.206mm)(14.319mm,52.206mm) on Component Side And Track (14.378mm,52.143mm)(15.561mm,52.143mm) on Component Side
Clearance Constraint: (0.168mm < 0.178mm) Between Track (50.046mm,45.231mm)(52.371mm,45.231mm) on Component Side And Via (51.777mm,44.619mm) from Component Side to Solder Side
Clearance Constraint: (Collision < 0.178mm) Between Track (7.499mm,52.206mm)(8.682mm,52.206mm) on Component Side And Track (8.682mm,52.192mm)(10.769mm,52.192mm) on Component Side
Clearance Constraint: (0.162mm < 0.178mm) Between Track (72.679mm,50.886mm)(74.704mm,48.861mm) on Component Side And Via (73.711mm,48.997mm) from Component Side to Solder Side
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Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net L-OUT Between Pad J12-3(4.294mm,6.938mm) on Multi-Layer And Track (21.429mm,6.938mm)(21.798mm,6.569mm) on Layer 3
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Un-Connected Pin Constraint ( (All) )
Un-Connected Pin Constraint: Pad J8-4(88.363mm,50.891mm) on Component Side
Un-Connected Pin Constraint: Pad U1-2(45.146mm,46.731mm) on Component Side
Un-Connected Pin Constraint: Pad U1-28(46.096mm,48.181mm) on Component Side
Un-Connected Pin Constraint: Pad U1-3(45.146mm,46.231mm) on Component Side
Un-Connected Pin Constraint: Pad U1-6(45.146mm,44.731mm) on Component Side
Un-Connected Pin Constraint: Pad U1-7(45.146mm,44.231mm) on Component Side
Un-Connected Pin Constraint: Pad U1-8(46.096mm,43.281mm) on Component Side
Un-Connected Pin Constraint: Pad U1-9(46.596mm,43.281mm) on Component Side
Un-Connected Pin Constraint: Pad U2-7(59.747mm,18.781mm) on Component Side
Un-Connected Pin Constraint: Pad U7-1(65.083mm,47.521mm) on Component Side
Un-Connected Pin Constraint: Pad U7-5(67.283mm,47.521mm) on Component Side
Un-Connected Pin Constraint: Pad U9-14(77.9mm,49.811mm) on Component Side
Un-Connected Pin Constraint: Pad U9-15(77.25mm,49.811mm) on Component Side
Un-Connected Pin Constraint: Pad U9-6(77.25mm,45.961mm) on Component Side
Un-Connected Pin Constraint: Pad U9-7(77.9mm,45.961mm) on Component Side
Un-Connected Pin Constraint: Pad U9-8(78.55mm,45.961mm) on Component Side
Un-Connected Pin Constraint: Pad U9-9(79.5mm,46.911mm) on Component Side
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Modified Polygon (Allow modified: No), (Allow shelved: No)
Modified Polygon: Polygon Shelved (Component Side-No Net) on Component Side
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Width Constraint (Min=0.254mm) (Max=1.524mm) (Preferred=0.254mm) (InNet('GND'))
Width Constraint: Track (48.444mm,14.645mm)(48.444mm,15.57mm) on Component Side Actual Width = 0.762mm, Target Width = 0.508mm
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SMD To Corner (Distance=0.1mm) (All)
SMD To Corner Constraint: (0.009mm < 0.1mm) Between Pad RS2-1(48.396mm,15.745mm) on Component Side And Track (48.396mm,15.745mm)(48.396mm,16.208mm) on Component Side Actual Distance = 0.009mm
SMD To Corner Constraint: (0.072mm < 0.1mm) Between Pad U10-8(72.992mm,37.524mm) on Component Side And Track (72.139mm,37.524mm)(72.992mm,37.524mm) on Component Side Actual Distance = 0.072mm
SMD To Corner Constraint: (0.029mm < 0.1mm) Between Pad U2-12(64.697mm,21.321mm) on Component Side And Track (64.697mm,21.321mm)(65.712mm,21.321mm) on Component Side Actual Distance = 0.029mm
SMD To Corner Constraint: (0.067mm < 0.1mm) Between Pad U8-4(63.834mm,34.647mm) on Component Side And Track (63.834mm,34.647mm)(64.551mm,34.647mm) on Component Side Actual Distance = 0.067mm
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Minimum Annular Ring (Minimum=0.15mm) (All)
Minimum Annular Ring: (0.05mm < 0.15mm) Pad J8-(88.556mm,47.747mm) on Multi-Layer (Annular Ring=0.05mm) On (Top Layer)
Minimum Annular Ring: (0.05mm < 0.15mm) Pad J8-(88.564mm,52.743mm) on Multi-Layer (Annular Ring=0.05mm) On (Top Layer)
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Acute Angle Constraint [Tracks Only] (Minimum=90.000) (All)
Acute Angle Constraint: (45.000 < 90.000) Between Track (70.509mm,24.104mm)(70.76mm,23.853mm) on Component Side And Track (70.76mm,23.233mm)(70.76mm,23.853mm) on Component Side (Angle = 45.000)
Acute Angle Constraint: (90.000 < 90.000) Between Track (65.525mm,32.866mm)(65.525mm,33.673mm) on Component Side And Track (65.525mm,32.866mm)(67.017mm,32.866mm) on Component Side (Angle = 90.000)
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Net Antennae (Tolerance=0.003mm) (All)
Net Antennae: Via (55.118mm,25.845mm) from Component Side to Solder Side
Net Antennae: Via (55.118mm,26.594mm) from Component Side to Solder Side
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Board Clearance Constraint (Gap=0mm) (OnLayer('Top Overlay','Bottom Overlay'))
Board Outline Clearance(Outline Edge): (0.188mm < 0.2mm) Between Board Edge And Text "LED4" (89.992mm,10.897mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.094mm < 0.2mm) Between Board Edge And Track (0.194mm,19.538mm)(7.894mm,19.538mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.094mm < 0.2mm) Between Board Edge And Track (0.194mm,33.492mm)(0.194mm,48.692mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.094mm < 0.2mm) Between Board Edge And Track (0.194mm,33.492mm)(7.894mm,33.492mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.094mm < 0.2mm) Between Board Edge And Track (0.194mm,4.338mm)(0.194mm,19.538mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.094mm < 0.2mm) Between Board Edge And Track (0.194mm,4.338mm)(7.894mm,4.338mm) on Top Overlay
Board Outline Clearance(Outline Edge): (0.094mm < 0.2mm) Between Board Edge And Track (0.194mm,48.692mm)(7.894mm,48.692mm) on Top Overlay
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